Resource efficient implementation of low power MB-OFDM PHY baseband modem with highly parallel architecture

Seok Joong Hwang, Youngsun Han, Seon Wook Kim, Jongsun Park, Byung Gueon Min

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The multi-band orthogonal frequency-division multiplexing modem needs to process large amount of computations in short time for support of high data rates, i.e., up to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi-way parallel architecture has been proposed. But the use of the high degree parallel architecture would increase chip resource significantly, thus a resource efficient design is essential. In this paper, we introduce several novel optimization techniques for resource efficient implementation of the baseband modem which has highly, i.e., 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and algorithm reconstruction for a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization technique could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of the entire baseband modem were about 785 kgates and less than 381 mW at 66 MHz clock rate, respectively.

Original languageEnglish
Article number5776728
Pages (from-to)1248-1261
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number7
DOIs
Publication statusPublished - 2012

Keywords

  • Baseband modem
  • multi-band orthogonal frequency-division multiplexing (MB-OFDM)
  • parallel architecture
  • resource optimization
  • ultra wideband (UWB)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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