Abstract
The multi-band orthogonal frequency-division multiplexing modem needs to process large amount of computations in short time for support of high data rates, i.e., up to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi-way parallel architecture has been proposed. But the use of the high degree parallel architecture would increase chip resource significantly, thus a resource efficient design is essential. In this paper, we introduce several novel optimization techniques for resource efficient implementation of the baseband modem which has highly, i.e., 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and algorithm reconstruction for a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization technique could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of the entire baseband modem were about 785 kgates and less than 381 mW at 66 MHz clock rate, respectively.
| Original language | English |
|---|---|
| Article number | 5776728 |
| Pages (from-to) | 1248-1261 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 20 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 2012 Jan 1 |
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Keywords
- Baseband modem
- multi-band orthogonal frequency-division multiplexing (MB-OFDM)
- parallel architecture
- resource optimization
- ultra wideband (UWB)
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
Cite this
Resource efficient implementation of low power MB-OFDM PHY baseband modem with highly parallel architecture. / Hwang, Seok Joong; Han, Youngsun; Kim, Seon Wook; Park, Jongsun; Min, Byung Gueon.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 7, 5776728, 01.01.2012, p. 1248-1261.Research output: Contribution to journal › Article
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TY - JOUR
T1 - Resource efficient implementation of low power MB-OFDM PHY baseband modem with highly parallel architecture
AU - Hwang, Seok Joong
AU - Han, Youngsun
AU - Kim, Seon Wook
AU - Park, Jongsun
AU - Min, Byung Gueon
PY - 2012/1/1
Y1 - 2012/1/1
N2 - The multi-band orthogonal frequency-division multiplexing modem needs to process large amount of computations in short time for support of high data rates, i.e., up to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi-way parallel architecture has been proposed. But the use of the high degree parallel architecture would increase chip resource significantly, thus a resource efficient design is essential. In this paper, we introduce several novel optimization techniques for resource efficient implementation of the baseband modem which has highly, i.e., 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and algorithm reconstruction for a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization technique could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of the entire baseband modem were about 785 kgates and less than 381 mW at 66 MHz clock rate, respectively.
AB - The multi-band orthogonal frequency-division multiplexing modem needs to process large amount of computations in short time for support of high data rates, i.e., up to 480 Mbps. In order to satisfy the performance requirement while reducing power consumption, a multi-way parallel architecture has been proposed. But the use of the high degree parallel architecture would increase chip resource significantly, thus a resource efficient design is essential. In this paper, we introduce several novel optimization techniques for resource efficient implementation of the baseband modem which has highly, i.e., 8-way, parallel architecture, such as new processing structures for a (de)interleaver and a packet synchronizer and algorithm reconstruction for a carrier frequency offset compensator. Also, we describe how to efficiently design several other components. The detailed analysis shows that our optimization technique could reduce the gate count by 27.6% on average, while none of techniques degraded the overall system performance. With 0.18-μm CMOS process, the gate count and power consumption of the entire baseband modem were about 785 kgates and less than 381 mW at 66 MHz clock rate, respectively.
KW - Baseband modem
KW - multi-band orthogonal frequency-division multiplexing (MB-OFDM)
KW - parallel architecture
KW - resource optimization
KW - ultra wideband (UWB)
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U2 - 10.1109/TVLSI.2011.2148132
DO - 10.1109/TVLSI.2011.2148132
M3 - Article
AN - SCOPUS:84862007094
VL - 20
SP - 1248
EP - 1261
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 7
M1 - 5776728
ER -