Revisited parameter extraction methodology for electrical characterization of junctionless transistors

D. Y. Jeon; S. J. Park; M. Mouis; M. Berthomé; S. Barraud; G. T. Kim; G. Ghibaudo

doi:10.1016/j.sse.2013.02.047

Revisited parameter extraction methodology for electrical characterization of junctionless transistors

D. Y. Jeon, S. J. Park, M. Mouis, M. Berthomé, S. Barraud, G. T. Kim, G. Ghibaudo

Research output: Contribution to journal › Article

60 Citations (Scopus)

Abstract

Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.

Original language	English
Pages (from-to)	86-93
Number of pages	8
Journal	Solid-State Electronics
Volume	90
DOIs	https://doi.org/10.1016/j.sse.2013.02.047
Publication status	Published - 2013

Keywords

Channel doping level
Drain induced barrier lowering (DIBL)
Flat-band voltage (V)
Junctionless transistors (JLTs)
Low field mobility (μ)
Threshold voltage (V)

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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Jeon, D. Y., Park, S. J., Mouis, M., Berthomé, M., Barraud, S., Kim, G. T., & Ghibaudo, G. (2013). Revisited parameter extraction methodology for electrical characterization of junctionless transistors. Solid-State Electronics, 90, 86-93. https://doi.org/10.1016/j.sse.2013.02.047

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AU - Kim, G. T.

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