Runtime parallelization of legacy code on a transactional memory system

Matthew DeVuyst, Dean M. Tullsen, Seon Wook Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

This paper proposes a new runtime parallelization technique, based on a dynamic optimization framework, to automatically parallelize single-threaded legacy programs. It heavily leverages the optimistic concurrency of transactional memory. This work addresses a number of challenges posed by this type of parallelization and quantifies the trade-offs of some of the design decisions, such as how to select good loops for parallelization, how to partition the iteration space among parallel threads, how to handle loop-carried dependencies, and how to transition from serial to parallel execution and back. The simulated implementation of runtime parallelization shows a potential speedup of 1.36 for the NAS benchmarks and a 1.34 speedup for the SPEC 2000 CPU floating point benchmarks when using two cores for parallel execution.

Original languageEnglish
Title of host publicationHiPEAC'11 - Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Pages127-136
Number of pages10
DOIs
Publication statusPublished - 2011
Event6th International Conference on High Performance and Embedded Architectures and Compilers, HiPEAC'11 - Heraklion, Crete, Greece
Duration: 2011 Jan 242011 Jan 26

Publication series

NameHiPEAC'11 - Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers

Other

Other6th International Conference on High Performance and Embedded Architectures and Compilers, HiPEAC'11
CountryGreece
CityHeraklion, Crete
Period11/1/2411/1/26

Keywords

  • Dynamic optimization
  • Parallelization
  • Transactional memory

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    DeVuyst, M., Tullsen, D. M., & Kim, S. W. (2011). Runtime parallelization of legacy code on a transactional memory system. In HiPEAC'11 - Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers (pp. 127-136). (HiPEAC'11 - Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers). https://doi.org/10.1145/1944862.1944882