Selective wordline voltage boosting for caches to manage yield under process variations

Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
Pages57-62
Number of pages6
Publication statusPublished - 2009 Nov 10
Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
Duration: 2009 Jul 262009 Jul 31

Other

Other2009 46th ACM/IEEE Design Automation Conference, DAC 2009
CountryUnited States
CitySan Francisco, CA
Period09/7/2609/7/31

Fingerprint

Process Variation
Boosting
Cache
Voltage
Electric potential
Electric power utilization
Chip
Fluctuations
Power Consumption
Latency
Eliminate
High Performance
Scaling
Line
Energy

Keywords

  • Access time failure
  • Cache
  • Process variations
  • Selective wordline voltage boosting
  • Yield

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

Cite this

Pan, Y., Kong, J., Ozdemir, S., Memik, G., & Jung, S. W. (2009). Selective wordline voltage boosting for caches to manage yield under process variations. In Proceedings - Design Automation Conference (pp. 57-62). [5227200]

Selective wordline voltage boosting for caches to manage yield under process variations. / Pan, Yan; Kong, Joonho; Ozdemir, Serkan; Memik, Gokhan; Jung, Sung Woo.

Proceedings - Design Automation Conference. 2009. p. 57-62 5227200.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pan, Y, Kong, J, Ozdemir, S, Memik, G & Jung, SW 2009, Selective wordline voltage boosting for caches to manage yield under process variations. in Proceedings - Design Automation Conference., 5227200, pp. 57-62, 2009 46th ACM/IEEE Design Automation Conference, DAC 2009, San Francisco, CA, United States, 09/7/26.
Pan Y, Kong J, Ozdemir S, Memik G, Jung SW. Selective wordline voltage boosting for caches to manage yield under process variations. In Proceedings - Design Automation Conference. 2009. p. 57-62. 5227200
Pan, Yan ; Kong, Joonho ; Ozdemir, Serkan ; Memik, Gokhan ; Jung, Sung Woo. / Selective wordline voltage boosting for caches to manage yield under process variations. Proceedings - Design Automation Conference. 2009. pp. 57-62
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