Abstract
One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - Design Automation Conference |
| Pages | 57-62 |
| Number of pages | 6 |
| Publication status | Published - 2009 Nov 10 |
| Event | 2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States Duration: 2009 Jul 26 → 2009 Jul 31 |
Other
| Other | 2009 46th ACM/IEEE Design Automation Conference, DAC 2009 |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 09/7/26 → 09/7/31 |
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Keywords
- Access time failure
- Cache
- Process variations
- Selective wordline voltage boosting
- Yield
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modelling and Simulation
Cite this
Selective wordline voltage boosting for caches to manage yield under process variations. / Pan, Yan; Kong, Joonho; Ozdemir, Serkan; Memik, Gokhan; Jung, Sung Woo.
Proceedings - Design Automation Conference. 2009. p. 57-62 5227200.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Selective wordline voltage boosting for caches to manage yield under process variations
AU - Pan, Yan
AU - Kong, Joonho
AU - Ozdemir, Serkan
AU - Memik, Gokhan
AU - Jung, Sung Woo
PY - 2009/11/10
Y1 - 2009/11/10
N2 - One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.
AB - One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.
KW - Access time failure
KW - Cache
KW - Process variations
KW - Selective wordline voltage boosting
KW - Yield
UR - http://www.scopus.com/inward/record.url?scp=70350710800&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70350710800&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:70350710800
SN - 9781605584973
SP - 57
EP - 62
BT - Proceedings - Design Automation Conference
ER -