TY - GEN
T1 - Selective wordline voltage boosting for caches to manage yield under process variations
AU - Pan, Yan
AU - Kong, Joonho
AU - Ozdemir, Serkan
AU - Memik, Gokhan
AU - Sung, Woo Chung
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2009
Y1 - 2009
N2 - One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.
AB - One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.
KW - Access time failure
KW - Cache
KW - Process variations
KW - Selective wordline voltage boosting
KW - Yield
UR - http://www.scopus.com/inward/record.url?scp=70350710800&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70350710800&partnerID=8YFLogxK
U2 - 10.1145/1629911.1629929
DO - 10.1145/1629911.1629929
M3 - Conference contribution
AN - SCOPUS:70350710800
SN - 9781605584973
T3 - Proceedings - Design Automation Conference
SP - 57
EP - 62
BT - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Y2 - 26 July 2009 through 31 July 2009
ER -