TY - GEN
T1 - Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors
AU - Jeon, Dae Young
AU - Park, So Jeong
AU - Mouis, Mireille
AU - Barraud, Sylvain
AU - Kim, Gyu Tae
AU - Ghibaudo, Gerard
N1 - Funding Information:
This work was supported in part by the European Union 7th Framework Program Project SQWIRE under Grant 257111, in part by the Korea Institute of Science and Technology (KIST) Institutional Program, in part by the National Research Foundation of Korea under Grants NRF- 2016R1A6A3A11933511, NRF-2017M3D9A1073924, and NRF-2017M3A7B4049167, and in part by the Korea University Grant.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on Vgband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.
AB - Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on Vgband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.
KW - back biasing effects
KW - junctionless transistors
KW - numerical simulation
KW - series resistance
UR - http://www.scopus.com/inward/record.url?scp=85083160657&partnerID=8YFLogxK
U2 - 10.1109/EUROSOI-ULIS45800.2019.9041921
DO - 10.1109/EUROSOI-ULIS45800.2019.9041921
M3 - Conference contribution
AN - SCOPUS:85083160657
T3 - 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
BT - 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
Y2 - 1 April 2019 through 3 April 2019
ER -