Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

Dae Young Jeon; So Jeong Park; Mireille Mouis; Sylvain Barraud; Gyu Tae Kim; Gerard Ghibaudo

doi:10.1109/EUROSOI-ULIS45800.2019.9041921

Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gerard Ghibaudo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (V_gb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (V_th) and flat-band voltage (V_fb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on V_gband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable R_sd effects. The R_sdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.

Original language	English
Title of host publication	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728116587
DOIs	https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921
Publication status	Published - 2019 Apr
Event	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 - Grenoble, France Duration: 2019 Apr 1 → 2019 Apr 3

Publication series

Name	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019

Conference

Conference	2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
Country	France
City	Grenoble
Period	19/4/1 → 19/4/3

Keywords

back biasing effects
junctionless transistors
numerical simulation
series resistance

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EUROSOI-ULIS45800.2019.9041921

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Jeon, D. Y., Park, S. J., Mouis, M., Barraud, S., Kim, G. T., & Ghibaudo, G. (2019). Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. In 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 [9041921] (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921

Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. / Jeon, Dae Young; Park, So Jeong; Mouis, Mireille; Barraud, Sylvain; Kim, Gyu Tae; Ghibaudo, Gerard.

2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9041921 (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jeon, DY, Park, SJ, Mouis, M, Barraud, S, Kim, GT & Ghibaudo, G 2019, Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. in 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019., 9041921, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019, Institute of Electrical and Electronics Engineers Inc., 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019, Grenoble, France, 19/4/1. https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921

Jeon DY, Park SJ, Mouis M, Barraud S, Kim GT, Ghibaudo G. Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. In 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 9041921. (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019). https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041921

Jeon, Dae Young ; Park, So Jeong ; Mouis, Mireille ; Barraud, Sylvain ; Kim, Gyu Tae ; Ghibaudo, Gerard. / Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors. 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019).

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