Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gerard Ghibaudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on Vgband back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsdwas extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.

Original languageEnglish
Title of host publication2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728116587
DOIs
Publication statusPublished - 2019 Apr
Event2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019 - Grenoble, France
Duration: 2019 Apr 12019 Apr 3

Publication series

Name2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019

Conference

Conference2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2019
CountryFrance
CityGrenoble
Period19/4/119/4/3

Keywords

  • back biasing effects
  • junctionless transistors
  • numerical simulation
  • series resistance

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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