SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps

M. Khater, Jae-Sung Rieh, T. Adam, A. Chinthakindi, J. Johnson, R. Krishnasamy, M. Meghelli, F. Pagette, D. Sanderson, C. Schnabel, K. T. Schonenberg, P. Smith, K. Stein, A. Stricker, S. J. Jeng, D. Ahlgren, G. Freeman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

81 Citations (Scopus)

Abstract

This work reports on SiGe HBT technology withf max and f T of 350 GHz and 300 GHz, respectively, and a gate delay below 3.3 ps. This is the highest reported speed for any Si-based transistor in terms of combined performance of f max and f T both of which exhibit 300 GHz and above. Associated BV CEO and BV CBO are measured to be 1.7 V and 5.6 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f max and f T values are also discussed.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
Pages247-250
Number of pages4
Publication statusPublished - 2004
Externally publishedYes
EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
Duration: 2004 Dec 132004 Dec 15

Other

OtherIEEE International Electron Devices Meeting, 2004 IEDM
CountryUnited States
CitySan Francisco, CA
Period04/12/1304/12/15

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Heterojunction bipolar transistors
Transistors

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Khater, M., Rieh, J-S., Adam, T., Chinthakindi, A., Johnson, J., Krishnasamy, R., ... Freeman, G. (2004). SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps In Technical Digest - International Electron Devices Meeting, IEDM (pp. 247-250)

SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps . / Khater, M.; Rieh, Jae-Sung; Adam, T.; Chinthakindi, A.; Johnson, J.; Krishnasamy, R.; Meghelli, M.; Pagette, F.; Sanderson, D.; Schnabel, C.; Schonenberg, K. T.; Smith, P.; Stein, K.; Stricker, A.; Jeng, S. J.; Ahlgren, D.; Freeman, G.

Technical Digest - International Electron Devices Meeting, IEDM. 2004. p. 247-250.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Khater, M, Rieh, J-S, Adam, T, Chinthakindi, A, Johnson, J, Krishnasamy, R, Meghelli, M, Pagette, F, Sanderson, D, Schnabel, C, Schonenberg, KT, Smith, P, Stein, K, Stricker, A, Jeng, SJ, Ahlgren, D & Freeman, G 2004, SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps in Technical Digest - International Electron Devices Meeting, IEDM. pp. 247-250, IEEE International Electron Devices Meeting, 2004 IEDM, San Francisco, CA, United States, 04/12/13.
Khater M, Rieh J-S, Adam T, Chinthakindi A, Johnson J, Krishnasamy R et al. SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps In Technical Digest - International Electron Devices Meeting, IEDM. 2004. p. 247-250
Khater, M. ; Rieh, Jae-Sung ; Adam, T. ; Chinthakindi, A. ; Johnson, J. ; Krishnasamy, R. ; Meghelli, M. ; Pagette, F. ; Sanderson, D. ; Schnabel, C. ; Schonenberg, K. T. ; Smith, P. ; Stein, K. ; Stricker, A. ; Jeng, S. J. ; Ahlgren, D. ; Freeman, G. / SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps Technical Digest - International Electron Devices Meeting, IEDM. 2004. pp. 247-250
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AU - Rieh, Jae-Sung

AU - Adam, T.

AU - Chinthakindi, A.

AU - Johnson, J.

AU - Krishnasamy, R.

AU - Meghelli, M.

AU - Pagette, F.

AU - Sanderson, D.

AU - Schnabel, C.

AU - Schonenberg, K. T.

AU - Smith, P.

AU - Stein, K.

AU - Stricker, A.

AU - Jeng, S. J.

AU - Ahlgren, D.

AU - Freeman, G.

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AB - This work reports on SiGe HBT technology withf max and f T of 350 GHz and 300 GHz, respectively, and a gate delay below 3.3 ps. This is the highest reported speed for any Si-based transistor in terms of combined performance of f max and f T both of which exhibit 300 GHz and above. Associated BV CEO and BV CBO are measured to be 1.7 V and 5.6 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f max and f T values are also discussed.

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