Simulation of serpentine trace of DQ PCB layout for DDR3 applications

Baekseok Ko; Joowon Kim; Kihun Oh; Chan Keun Kwon; Soo-Won Kim

doi:10.1109/ICCE.2016.7430509

Simulation of serpentine trace of DQ PCB layout for DDR3 applications

Baekseok Ko, Joowon Kim, Kihun Oh, Chan Keun Kwon, Soo-Won Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.

Original language	English
Title of host publication	2016 IEEE International Conference on Consumer Electronics, ICCE 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	27-28
Number of pages	2
ISBN (Print)	9781467383646
DOIs	https://doi.org/10.1109/ICCE.2016.7430509
Publication status	Published - 2016 Mar 10
Event	IEEE International Conference on Consumer Electronics, ICCE 2016 - Las Vegas, United States Duration: 2016 Jan 7 → 2016 Jan 11

Other

Other	IEEE International Conference on Consumer Electronics, ICCE 2016
Country/Territory	United States
City	Las Vegas
Period	16/1/7 → 16/1/11

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering

Access to Document

10.1109/ICCE.2016.7430509

Cite this

Ko, B, Kim, J, Oh, K, Kwon, CK & Kim, S-W 2016, Simulation of serpentine trace of DQ PCB layout for DDR3 applications. in 2016 IEEE International Conference on Consumer Electronics, ICCE 2016., 7430509, Institute of Electrical and Electronics Engineers Inc., pp. 27-28, IEEE International Conference on Consumer Electronics, ICCE 2016, Las Vegas, United States, 16/1/7. https://doi.org/10.1109/ICCE.2016.7430509

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title = "Simulation of serpentine trace of DQ PCB layout for DDR3 applications",

abstract = "This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.",

author = "Baekseok Ko and Joowon Kim and Kihun Oh and Kwon, {Chan Keun} and Soo-Won Kim",

year = "2016",

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doi = "10.1109/ICCE.2016.7430509",

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AU - Kim, Joowon

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AU - Kim, Soo-Won

PY - 2016/3/10

Y1 - 2016/3/10

N2 - This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.

AB - This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.

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M3 - Conference contribution

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SN - 9781467383646

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BT - 2016 IEEE International Conference on Consumer Electronics, ICCE 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Consumer Electronics, ICCE 2016

Y2 - 7 January 2016 through 11 January 2016

ER -

Simulation of serpentine trace of DQ PCB layout for DDR3 applications

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