Simulation of serpentine trace of DQ PCB layout for DDR3 applications

Baekseok Ko, Joowon Kim, Kihun Oh, Chan Keun Kwon, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents an analysis of a simulated serpentine signal line for a DDR3 memory interface. DDR implementation on a PCB should allow for the estimation of the figure except for the DQ length and impedance matching. To match the DQ timing specification in a PCB (printed circuit board), a serpentine line is simulated using an EM (electromagnetic) tool and DOE (design of experiments) analysis. In the same manner, the weight of a serpentine structure is quantified by comparing it with the other factors of PCB routing. The simulated factors prioritize the design of a memory interface in a system.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Consumer Electronics, ICCE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages27-28
Number of pages2
ISBN (Print)9781467383646
DOIs
Publication statusPublished - 2016 Mar 10
EventIEEE International Conference on Consumer Electronics, ICCE 2016 - Las Vegas, United States
Duration: 2016 Jan 72016 Jan 11

Other

OtherIEEE International Conference on Consumer Electronics, ICCE 2016
CountryUnited States
CityLas Vegas
Period16/1/716/1/11

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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  • Cite this

    Ko, B., Kim, J., Oh, K., Kwon, C. K., & Kim, S-W. (2016). Simulation of serpentine trace of DQ PCB layout for DDR3 applications. In 2016 IEEE International Conference on Consumer Electronics, ICCE 2016 (pp. 27-28). [7430509] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE.2016.7430509