Si+ ion implanted MPS bulk GaN diodes

Y. Irokawa; J. Kim; F. Ren; K. H. Baik; B. P. Gila; C. R. Abernathy; S. J. Pearton; C. C. Pan; G. T. Chen; J. I. Chyi; S. S. Park

doi:10.1016/j.sse.2003.09.018

Si⁺ ion implanted MPS bulk GaN diodes

Y. Irokawa, J. Kim, F. Ren, K. H. Baik, B. P. Gila, C. R. Abernathy, S. J. Pearton, C. C. Pan, G. T. Chen, J. I. Chyi, S. S. Park

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

The fabrication of GaN merged p-i-n/Schottky (MPS) diodes using Si ⁺ ion implantation into p-epi layers on bulk, free-standing GaN substrates is reported. Diode diameters from 50 to 500 μm were investigated. These initial MPS diodes show larger turn-on voltage (∼30 V) than the unimplanted p-i-n diodes (∼10 V) fabricated on the same wafer but lower reverse leakage current density. The Si⁺ implant activation efficiency is ∼25% for 1150 °C anneals, reaching ∼30% for 1200 °C anneals.

Original language	English
Pages (from-to)	827-830
Number of pages	4
Journal	Solid-State Electronics
Volume	48
Issue number	5
DOIs	https://doi.org/10.1016/j.sse.2003.09.018
Publication status	Published - 2004 May
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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@article{e532b51aaca24c7d9b29b3e60f462242,

title = "Si+ ion implanted MPS bulk GaN diodes",

abstract = "The fabrication of GaN merged p-i-n/Schottky (MPS) diodes using Si + ion implantation into p-epi layers on bulk, free-standing GaN substrates is reported. Diode diameters from 50 to 500 μm were investigated. These initial MPS diodes show larger turn-on voltage (∼30 V) than the unimplanted p-i-n diodes (∼10 V) fabricated on the same wafer but lower reverse leakage current density. The Si+ implant activation efficiency is ∼25% for 1150 °C anneals, reaching ∼30% for 1200 °C anneals.",

author = "Y. Irokawa and J. Kim and F. Ren and Baik, {K. H.} and Gila, {B. P.} and Abernathy, {C. R.} and Pearton, {S. J.} and Pan, {C. C.} and Chen, {G. T.} and Chyi, {J. I.} and Park, {S. S.}",

note = "Funding Information: The work at UF is partially supported by EPRI and NSF. The work at NCU is partially supported by the Ministry of Education of R.O.C. under the Program for Promoting Academic Excellence of Universities (890E-FA06-1-4) and the National Science Council of R.O.C. (NSC89-2215-E-008-031)",

year = "2004",

month = may,

doi = "10.1016/j.sse.2003.09.018",

language = "English",

volume = "48",

pages = "827--830",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

number = "5",

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TY - JOUR

T1 - Si+ ion implanted MPS bulk GaN diodes

AU - Irokawa, Y.

AU - Kim, J.

AU - Ren, F.

AU - Baik, K. H.

AU - Gila, B. P.

AU - Abernathy, C. R.

AU - Pearton, S. J.

AU - Pan, C. C.

AU - Chen, G. T.

AU - Chyi, J. I.

AU - Park, S. S.

N1 - Funding Information: The work at UF is partially supported by EPRI and NSF. The work at NCU is partially supported by the Ministry of Education of R.O.C. under the Program for Promoting Academic Excellence of Universities (890E-FA06-1-4) and the National Science Council of R.O.C. (NSC89-2215-E-008-031)

PY - 2004/5

Y1 - 2004/5

N2 - The fabrication of GaN merged p-i-n/Schottky (MPS) diodes using Si + ion implantation into p-epi layers on bulk, free-standing GaN substrates is reported. Diode diameters from 50 to 500 μm were investigated. These initial MPS diodes show larger turn-on voltage (∼30 V) than the unimplanted p-i-n diodes (∼10 V) fabricated on the same wafer but lower reverse leakage current density. The Si+ implant activation efficiency is ∼25% for 1150 °C anneals, reaching ∼30% for 1200 °C anneals.

AB - The fabrication of GaN merged p-i-n/Schottky (MPS) diodes using Si + ion implantation into p-epi layers on bulk, free-standing GaN substrates is reported. Diode diameters from 50 to 500 μm were investigated. These initial MPS diodes show larger turn-on voltage (∼30 V) than the unimplanted p-i-n diodes (∼10 V) fabricated on the same wafer but lower reverse leakage current density. The Si+ implant activation efficiency is ∼25% for 1150 °C anneals, reaching ∼30% for 1200 °C anneals.

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U2 - 10.1016/j.sse.2003.09.018

DO - 10.1016/j.sse.2003.09.018

M3 - Article

AN - SCOPUS:10744223191

VL - 48

SP - 827

EP - 830

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 5