Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

Jabeom Koo; Gil Su Kim; Junyoung Song; Kwan Weon Kim; Young Jung Choi; Chulwoo Kim

doi:10.1109/CICC.2009.5280735

Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

Jabeom Koo, Gil Su Kim, Junyoung Song, Kwan Weon Kim, Young Jung Choi, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm² and 0.015mm², respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.

Original language	English
Title of host publication	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages	717-720
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2009.5280735
Publication status	Published - 2009
Event	2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States Duration: 2009 Sep 13 → 2009 Sep 16

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Country	United States
City	San Jose, CA
Period	09/9/13 → 09/9/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2009.5280735

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Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. / Koo, Jabeom; Kim, Gil Su; Song, Junyoung; Kim, Kwan Weon; Choi, Young Jung; Kim, Chulwoo.

2009 IEEE Custom Integrated Circuits Conference, CICC '09. 2009. p. 717-720 5280735 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Koo, J, Kim, GS, Song, J, Kim, KW, Choi, YJ & Kim, C 2009, Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. in 2009 IEEE Custom Integrated Circuits Conference, CICC '09., 5280735, Proceedings of the Custom Integrated Circuits Conference, pp. 717-720, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 09/9/13. https://doi.org/10.1109/CICC.2009.5280735

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abstract = "The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.",

author = "Jabeom Koo and Kim, {Gil Su} and Junyoung Song and Kim, {Kwan Weon} and Choi, {Young Jung} and Chulwoo Kim",

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AB - The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.

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Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

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