Abstract
The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm 2 and 0.015mm 2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Custom Integrated Circuits Conference |
| Pages | 717-720 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2009 Dec 1 |
| Event | 2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States Duration: 2009 Sep 13 → 2009 Sep 16 |
Other
| Other | 2009 IEEE Custom Integrated Circuits Conference, CICC '09 |
|---|---|
| Country | United States |
| City | San Jose, CA |
| Period | 09/9/13 → 09/9/16 |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. / Koo, Jabeom; Kim, Gil Su; Song, Junyoung; Kim, Kwan Weon; Choi, Young Jung; Kim, Chulwoo.
Proceedings of the Custom Integrated Circuits Conference. 2009. p. 717-720 5280735.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application
AU - Koo, Jabeom
AU - Kim, Gil Su
AU - Song, Junyoung
AU - Kim, Kwan Weon
AU - Choi, Young Jung
AU - Kim, Chulwoo
PY - 2009/12/1
Y1 - 2009/12/1
N2 - The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm 2 and 0.015mm 2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.
AB - The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm 2 and 0.015mm 2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.
UR - http://www.scopus.com/inward/record.url?scp=74049133976&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74049133976&partnerID=8YFLogxK
U2 - 10.1109/CICC.2009.5280735
DO - 10.1109/CICC.2009.5280735
M3 - Conference contribution
AN - SCOPUS:74049133976
SN - 9781424440726
SP - 717
EP - 720
BT - Proceedings of the Custom Integrated Circuits Conference
ER -