Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors

Eun Ae Chung, Young Pil Kim, Min Chul Park, Kab Jin Nam, Sung Sam Lee, Ji Young Min, Giyoung Yang, Yu Gyun Shin, Siyoung Choi, Gyoyoung Jin, Joo Tae Moon, Sangsig Kim

Research output: Contribution to journalArticle

Abstract

The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying FowlerNordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.

Original languageEnglish
Article number5629430
Pages (from-to)81-83
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number1
DOIs
Publication statusPublished - 2011 Jan 1

Keywords

  • Cell transistor
  • charge pumping (CP)
  • interface traps
  • MOSFET
  • recessed-channel array transistor (RCAT)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Chung, E. A., Kim, Y. P., Park, M. C., Nam, K. J., Lee, S. S., Min, J. Y., Yang, G., Shin, Y. G., Choi, S., Jin, G., Moon, J. T., & Kim, S. (2011). Spatial distribution of interface traps in sub-50-nm recess-channel-type DRAM cell transistors. IEEE Electron Device Letters, 32(1), 81-83. [5629430]. https://doi.org/10.1109/LED.2010.2085416