Spin orbit torque device based stochastic multi-bit synapses for on-chip STDP learning

Gyuseong Kang; Yunho Jang; Jongsun Park

doi:10.1145/3218603.3218654

Spin orbit torque device based stochastic multi-bit synapses for on-chip STDP learning

Gyuseong Kang, Yunho Jang, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

As a large number of neurons and synapses are needed in spike neural network (SNN) design, emerging devices have been employed to implement synapses and neurons. In this paper, we present a stochastic multi-bit spin orbit torque (SOT) memory based synapse, where only one SOT device is switched for potentiation and depression using modified Gray code. The modified Gray code based approach needs only N devices to represent 2^N levels of synapse weights. Early read termination scheme is also adopted to reduce the power consumption of training process by turning off less associated neurons and its ADCs. For MNIST dataset, with comparable classification accuracy, the proposed SNN architecture using 3-bit synapse achieves 68.7% reduction of ADC overhead compared to the conventional 8-level synapse.

Original language	English
Title of host publication	ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781450357043
DOIs	https://doi.org/10.1145/3218603.3218654
Publication status	Published - 2018 Jul 23
Event	23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018 - Bellevue, United States Duration: 2018 Jul 23 → 2018 Jul 25

Other

Other	23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018
Country/Territory	United States
City	Bellevue
Period	18/7/23 → 18/7/25

Keywords

Neuromorphic processor
Spiking neural network
Spin orbit torque
STDP
Stochastic synapse

ASJC Scopus subject areas

Engineering(all)

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10.1145/3218603.3218654

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Spin orbit torque device based stochastic multi-bit synapses for on-chip STDP learning. / Kang, Gyuseong; Jang, Yunho; Park, Jongsun.

ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2018. a21.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kang, G, Jang, Y & Park, J 2018, Spin orbit torque device based stochastic multi-bit synapses for on-chip STDP learning. in ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design., a21, Institute of Electrical and Electronics Engineers Inc., 23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018, Bellevue, United States, 18/7/23. https://doi.org/10.1145/3218603.3218654

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abstract = "As a large number of neurons and synapses are needed in spike neural network (SNN) design, emerging devices have been employed to implement synapses and neurons. In this paper, we present a stochastic multi-bit spin orbit torque (SOT) memory based synapse, where only one SOT device is switched for potentiation and depression using modified Gray code. The modified Gray code based approach needs only N devices to represent 2N levels of synapse weights. Early read termination scheme is also adopted to reduce the power consumption of training process by turning off less associated neurons and its ADCs. For MNIST dataset, with comparable classification accuracy, the proposed SNN architecture using 3-bit synapse achieves 68.7% reduction of ADC overhead compared to the conventional 8-level synapse.",

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N2 - As a large number of neurons and synapses are needed in spike neural network (SNN) design, emerging devices have been employed to implement synapses and neurons. In this paper, we present a stochastic multi-bit spin orbit torque (SOT) memory based synapse, where only one SOT device is switched for potentiation and depression using modified Gray code. The modified Gray code based approach needs only N devices to represent 2N levels of synapse weights. Early read termination scheme is also adopted to reduce the power consumption of training process by turning off less associated neurons and its ADCs. For MNIST dataset, with comparable classification accuracy, the proposed SNN architecture using 3-bit synapse achieves 68.7% reduction of ADC overhead compared to the conventional 8-level synapse.

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Spin orbit torque device based stochastic multi-bit synapses for on-chip STDP learning

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