Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme

Taehwan Kim; Jongsun Park

doi:10.1109/ISOCC.2018.8649942

Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme

Taehwan Kim, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As a promising candidate for replacing CMOS-based memories, non-volatile magnetic memory has been on a rise. While Spin transfer torque random access memory (STT-RAM) is considered as most promising candidate, it still suffers from various shortcomings concerning write operation. As a result, spin orbit torque random access memory (SOT-RAM) is considered as next generation non-volatile magnetic memory, for it offers relatively better performance and lower power. Even though SOT-RAM shows various advantages over STT-RAM, to meet the power level of CMOS-based memories, significant reduction of write power is highly required. Therefore, in this paper, we propose novel technique for reducing write power of SOT-RAM with redundant write prevention and early write termination. For application of two techniques, self-verification scheme is exploited. Simulation results using 65nm CMOS technology show that up to 69.5% of write energy can be saved compared to the conventional write operation.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2018, ISOCC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	19-20
Number of pages	2
ISBN (Electronic)	9781538679609
DOIs	https://doi.org/10.1109/ISOCC.2018.8649942
Publication status	Published - 2019 Feb 22
Event	15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of Duration: 2018 Nov 12 → 2018 Nov 15

Publication series

Name	Proceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference	15th International SoC Design Conference, ISOCC 2018
Country/Territory	Korea, Republic of
City	Daegu
Period	18/11/12 → 18/11/15

Keywords

Spin-orbit torque(SOT)
Write power reduction

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2018.8649942

Cite this

Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. / Kim, Taehwan; Park, Jongsun.

Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 19-20 8649942 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, T & Park, J 2019, Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649942, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 19-20, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649942

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abstract = "As a promising candidate for replacing CMOS-based memories, non-volatile magnetic memory has been on a rise. While Spin transfer torque random access memory (STT-RAM) is considered as most promising candidate, it still suffers from various shortcomings concerning write operation. As a result, spin orbit torque random access memory (SOT-RAM) is considered as next generation non-volatile magnetic memory, for it offers relatively better performance and lower power. Even though SOT-RAM shows various advantages over STT-RAM, to meet the power level of CMOS-based memories, significant reduction of write power is highly required. Therefore, in this paper, we propose novel technique for reducing write power of SOT-RAM with redundant write prevention and early write termination. For application of two techniques, self-verification scheme is exploited. Simulation results using 65nm CMOS technology show that up to 69.5% of write energy can be saved compared to the conventional write operation.",

keywords = "Spin-orbit torque(SOT), Write power reduction",

author = "Taehwan Kim and Jongsun Park",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.; 15th International SoC Design Conference, ISOCC 2018 ; Conference date: 12-11-2018 Through 15-11-2018",

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N2 - As a promising candidate for replacing CMOS-based memories, non-volatile magnetic memory has been on a rise. While Spin transfer torque random access memory (STT-RAM) is considered as most promising candidate, it still suffers from various shortcomings concerning write operation. As a result, spin orbit torque random access memory (SOT-RAM) is considered as next generation non-volatile magnetic memory, for it offers relatively better performance and lower power. Even though SOT-RAM shows various advantages over STT-RAM, to meet the power level of CMOS-based memories, significant reduction of write power is highly required. Therefore, in this paper, we propose novel technique for reducing write power of SOT-RAM with redundant write prevention and early write termination. For application of two techniques, self-verification scheme is exploited. Simulation results using 65nm CMOS technology show that up to 69.5% of write energy can be saved compared to the conventional write operation.

AB - As a promising candidate for replacing CMOS-based memories, non-volatile magnetic memory has been on a rise. While Spin transfer torque random access memory (STT-RAM) is considered as most promising candidate, it still suffers from various shortcomings concerning write operation. As a result, spin orbit torque random access memory (SOT-RAM) is considered as next generation non-volatile magnetic memory, for it offers relatively better performance and lower power. Even though SOT-RAM shows various advantages over STT-RAM, to meet the power level of CMOS-based memories, significant reduction of write power is highly required. Therefore, in this paper, we propose novel technique for reducing write power of SOT-RAM with redundant write prevention and early write termination. For application of two techniques, self-verification scheme is exploited. Simulation results using 65nm CMOS technology show that up to 69.5% of write energy can be saved compared to the conventional write operation.

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Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme

Abstract

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Keywords

ASJC Scopus subject areas

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