Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme

Taehwan Kim, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As a promising candidate for replacing CMOS-based memories, non-volatile magnetic memory has been on a rise. While Spin transfer torque random access memory (STT-RAM) is considered as most promising candidate, it still suffers from various shortcomings concerning write operation. As a result, spin orbit torque random access memory (SOT-RAM) is considered as next generation non-volatile magnetic memory, for it offers relatively better performance and lower power. Even though SOT-RAM shows various advantages over STT-RAM, to meet the power level of CMOS-based memories, significant reduction of write power is highly required. Therefore, in this paper, we propose novel technique for reducing write power of SOT-RAM with redundant write prevention and early write termination. For application of two techniques, self-verification scheme is exploited. Simulation results using 65nm CMOS technology show that up to 69.5% of write energy can be saved compared to the conventional write operation.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2018, ISOCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages19-20
Number of pages2
ISBN (Electronic)9781538679609
DOIs
Publication statusPublished - 2019 Feb 22
Event15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of
Duration: 2018 Nov 122018 Nov 15

Publication series

NameProceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference15th International SoC Design Conference, ISOCC 2018
CountryKorea, Republic of
CityDaegu
Period18/11/1218/11/15

Fingerprint

Random access storage
Orbits
Torque
Data storage equipment

Keywords

  • Spin-orbit torque(SOT)
  • Write power reduction

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, T., & Park, J. (2019). Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 19-20). [8649942] (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649942

Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. / Kim, Taehwan; Park, Jongsun.

Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 19-20 8649942 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, T & Park, J 2019, Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649942, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 19-20, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649942
Kim T, Park J. Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. In Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 19-20. 8649942. (Proceedings - International SoC Design Conference 2018, ISOCC 2018). https://doi.org/10.1109/ISOCC.2018.8649942
Kim, Taehwan ; Park, Jongsun. / Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 19-20 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).
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