As a promising candidate for replacing CMOS-based memories, non-volatile magnetic memory has been on a rise. While Spin transfer torque random access memory (STT-RAM) is considered as most promising candidate, it still suffers from various shortcomings concerning write operation. As a result, spin orbit torque random access memory (SOT-RAM) is considered as next generation non-volatile magnetic memory, for it offers relatively better performance and lower power. Even though SOT-RAM shows various advantages over STT-RAM, to meet the power level of CMOS-based memories, significant reduction of write power is highly required. Therefore, in this paper, we propose novel technique for reducing write power of SOT-RAM with redundant write prevention and early write termination. For application of two techniques, self-verification scheme is exploited. Simulation results using 65nm CMOS technology show that up to 69.5% of write energy can be saved compared to the conventional write operation.