TY - JOUR
T1 - Static Random Access Memory Characteristics of Single-Gated Feedback Field-Effect Transistors
AU - Cho, Jinsun
AU - Lim, Doohyeok
AU - Woo, Sola
AU - Cho, Kyungah
AU - Kim, Sangsig
N1 - Funding Information:
Manuscript received September 6, 2018; revised October 24, 2018 and November 9, 2018; accepted November 9, 2018. Date of publication December 3, 2018; date of current version December 24, 2018. This work was supported in part by the National Research Foundation of Korea Grant funded by the Korean Government (MSIP) under Grant NRF-2016R1E1A1A02920171, in part by the Ministry of Trade, Industry and Energy, South Korea, through the Industrial Strategic Technology Development Program (development of fabrication and device structure of feedback Si channel 1T-SRAM for artificial intelligence) under Grant 10067791, and in part by the Brain Korea 21 Plus Project in 2018. The review of this paper was arranged by Editor P.-Y. Du. (Corresponding author: Sangsig Kim.) J. Cho is with the Department of Semiconductor Systems Engineering, Korea University, Seoul 02841, South Korea.
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2019/1
Y1 - 2019/1
N2 - In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of 0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding '1' and negligible for holding '0.' Moreover, our SRAM array shows reliable 3 × 3 array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.
AB - In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of 0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding '1' and negligible for holding '0.' Moreover, our SRAM array shows reliable 3 × 3 array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.
KW - Feedback field-effect transistors (FBFETs)
KW - positive feedback loop
KW - static random access memory (SRAM)
KW - transient simulation
UR - http://www.scopus.com/inward/record.url?scp=85058073320&partnerID=8YFLogxK
U2 - 10.1109/TED.2018.2881965
DO - 10.1109/TED.2018.2881965
M3 - Article
AN - SCOPUS:85058073320
SN - 0018-9383
VL - 66
SP - 413
EP - 419
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 1
M1 - 8556508
ER -