Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device

Yu Jin Pyo, Soo Han Choi, Chul Hong Park, Sang Hoon Lee, Moon Hyun Yoo, Gyu-Tae Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and exposing sequence of two masks to avoid the electrical degradation.

Original languageEnglish
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
Volume7974
DOIs
Publication statusPublished - 2011 May 16
EventDesign for Manufacturability through Design-Process Integration V - San Jose, CA, United States
Duration: 2011 Mar 22011 Mar 3

Other

OtherDesign for Manufacturability through Design-Process Integration V
CountryUnited States
CitySan Jose, CA
Period11/3/211/3/3

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Keywords

  • Double patterning
  • DRAM
  • Electrical performance
  • Hotspot
  • Process specification

ASJC Scopus subject areas

  • Applied Mathematics
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

Cite this

Pyo, Y. J., Choi, S. H., Park, C. H., Lee, S. H., Yoo, M. H., & Kim, G-T. (2011). Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device. In Proceedings of SPIE - The International Society for Optical Engineering (Vol. 7974). [797413] https://doi.org/10.1117/12.869978