Abstract
Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 |
| Publisher | IEEE Computer Society |
| Pages | 74-79 |
| Number of pages | 6 |
| Volume | 2017-July |
| ISBN (Electronic) | 9781509067626 |
| DOIs | |
| Publication status | Published - 2017 Jul 20 |
| Event | 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: 2017 Jul 3 → 2017 Jul 5 |
Other
| Other | 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 |
|---|---|
| Country | Germany |
| City | Bochum, North Rhine-Westfalia |
| Period | 17/7/3 → 17/7/5 |
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Keywords
- BDD
- countermeasure
- side channel attack
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering
Cite this
STBC : Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. / Kim, Hyunmin; Hong, Seokhie; Preneel, Bart; Verbauwhede, Ingrid.
Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Vol. 2017-July IEEE Computer Society, 2017. p. 74-79 7987498.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - STBC
T2 - Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay
AU - Kim, Hyunmin
AU - Hong, Seokhie
AU - Preneel, Bart
AU - Verbauwhede, Ingrid
PY - 2017/7/20
Y1 - 2017/7/20
N2 - Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.
AB - Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.
KW - BDD
KW - countermeasure
KW - side channel attack
UR - http://www.scopus.com/inward/record.url?scp=85027266233&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85027266233&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2017.22
DO - 10.1109/ISVLSI.2017.22
M3 - Conference contribution
AN - SCOPUS:85027266233
VL - 2017-July
SP - 74
EP - 79
BT - Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
PB - IEEE Computer Society
ER -