STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay

Hyunmin Kim, Seokhie Hong, Bart Preneel, Ingrid Verbauwhede

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
PublisherIEEE Computer Society
Pages74-79
Number of pages6
Volume2017-July
ISBN (Electronic)9781509067626
DOIs
Publication statusPublished - 2017 Jul 20
Event2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany
Duration: 2017 Jul 32017 Jul 5

Other

Other2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
CountryGermany
CityBochum, North Rhine-Westfalia
Period17/7/317/7/5

Fingerprint

Binary decision diagrams
Networks (circuits)
Rails
Logic circuits
Integrated circuits
Physical properties
Side channel attack

Keywords

  • BDD
  • countermeasure
  • side channel attack

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Kim, H., Hong, S., Preneel, B., & Verbauwhede, I. (2017). STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. In Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (Vol. 2017-July, pp. 74-79). [7987498] IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.22

STBC : Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. / Kim, Hyunmin; Hong, Seokhie; Preneel, Bart; Verbauwhede, Ingrid.

Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Vol. 2017-July IEEE Computer Society, 2017. p. 74-79 7987498.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, H, Hong, S, Preneel, B & Verbauwhede, I 2017, STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. in Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. vol. 2017-July, 7987498, IEEE Computer Society, pp. 74-79, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 17/7/3. https://doi.org/10.1109/ISVLSI.2017.22
Kim H, Hong S, Preneel B, Verbauwhede I. STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. In Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Vol. 2017-July. IEEE Computer Society. 2017. p. 74-79. 7987498 https://doi.org/10.1109/ISVLSI.2017.22
Kim, Hyunmin ; Hong, Seokhie ; Preneel, Bart ; Verbauwhede, Ingrid. / STBC : Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. Vol. 2017-July IEEE Computer Society, 2017. pp. 74-79
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