STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay

Hyunmin Kim; Seokhie Hong; Bart Preneel; Ingrid Verbauwhede

doi:10.1109/ISVLSI.2017.22

STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay

Hyunmin Kim, Seokhie Hong, Bart Preneel, Ingrid Verbauwhede

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.

Original language	English
Title of host publication	Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Editors	Ricardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
Publisher	IEEE Computer Society
Pages	74-79
Number of pages	6
ISBN (Electronic)	9781509067626
DOIs	https://doi.org/10.1109/ISVLSI.2017.22
Publication status	Published - 2017 Jul 20
Event	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: 2017 Jul 3 → 2017 Jul 5

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2017-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Other

Other	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Country	Germany
City	Bochum, North Rhine-Westfalia
Period	17/7/3 → 17/7/5

Keywords

BDD
countermeasure
side channel attack

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2017.22

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Kim, H., Hong, S., Preneel, B., & Verbauwhede, I. (2017). STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 74-79). [7987498] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.22

STBC : Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. / Kim, Hyunmin; Hong, Seokhie; Preneel, Bart; Verbauwhede, Ingrid.

Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. ed. / Ricardo Reis; Mircea Stan; Michael Huebner; Nikolaos Voros. IEEE Computer Society, 2017. p. 74-79 7987498 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, H, Hong, S, Preneel, B & Verbauwhede, I 2017, STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. in R Reis, M Stan, M Huebner & N Voros (eds), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017., 7987498, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2017-July, IEEE Computer Society, pp. 74-79, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 17/7/3. https://doi.org/10.1109/ISVLSI.2017.22

Kim H, Hong S, Preneel B, Verbauwhede I. STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. In Reis R, Stan M, Huebner M, Voros N, editors, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. IEEE Computer Society. 2017. p. 74-79. 7987498. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). https://doi.org/10.1109/ISVLSI.2017.22

Kim, Hyunmin ; Hong, Seokhie ; Preneel, Bart ; Verbauwhede, Ingrid. / STBC : Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. editor / Ricardo Reis ; Mircea Stan ; Michael Huebner ; Nikolaos Voros. IEEE Computer Society, 2017. pp. 74-79 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).

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N2 - Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.

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STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay

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