Substrate and layout engineering to suppress self-heating in floating body transistors

Self-heating (SH) has emerged as an important performance, variability, and reliability concern for floating body transistors (FB-FET), namely, extremely-thin-silicon-on-insulator (ETSOI), SOI-FinFET, gate-all-round NW-FET (GAA-FETs), etc. The floating body topology offers electrostatic control, but restricts heat outflow: apparently an intrinsic trade-off. In this paper, we trace the trajectory of heat flow in a broad range of transistors to show that the trade-off is not fundamental, and self-heating can be suppressed by novel device designs that ease thermal bottlenecks. Towards this goal, we (i) characterize SH in various FB-FETs with different channel materials (Si, Ge, InGaAs) by submicron thermo-reflectance imaging; (ii) identify universal features and common thermal bottlenecks across various transistor technologies, (iii) offer novel, technology-aware device design to ease the bottlenecks and reduce self-heating, and (iv) experimentally demonstrate the effectiveness of these strategies in suppressing self-heating. We conclude that thermal aware transistor design can suppress self-heating without compromising performance and electrostatic control of the transistor.