Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors

Effect of interface trap charge

B. H. Hong, N. Cho, S. J. Lee, Y. S. Yu, L. Choi, Y. C. Jung, K. H. Cho, K. H. Yeo, D. W. Kim, G. Y. Jin, K. S. Oh, D. Park, S. H. Song, Jae-Sung Rieh, S. W. Hwang

Research output: Contribution to journal › Article

19 Citations (Scopus)

Abstract

We measured and analyzed the subthreshold degradation of the gate-all-around (GAA) silicon nanowire field-effect transistors with the length of 300/500 nm and the radius of 5 nm. An analytical model incorporating the effect of interface traps quantitatively explained the measured subthreshold swing (SS) degradation. A simple electrostatic argument showed that the GAA device had smaller degradation of SS values than planar devices for the same interface trap densities.

Original languageEnglish
Article number5944946
Pages (from-to)1179-1181
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number9
DOIs
Publication statusPublished - 2011 Sep 1

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Silicon
Field effect transistors
Nanowires
Degradation
Analytical models
Electrostatics

Keywords

  • Gate-all-around (GAA)
  • interface trap charge
  • silicon nanowire field-effect transistor (SNWFET)
  • subthreshold degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Hong, B. H., Cho, N., Lee, S. J., Yu, Y. S., Choi, L., Jung, Y. C., ... Hwang, S. W. (2011). Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors: Effect of interface trap charge. IEEE Electron Device Letters, 32(9), 1179-1181. [5944946]. https://doi.org/10.1109/LED.2011.2159473

Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors : Effect of interface trap charge. / Hong, B. H.; Cho, N.; Lee, S. J.; Yu, Y. S.; Choi, L.; Jung, Y. C.; Cho, K. H.; Yeo, K. H.; Kim, D. W.; Jin, G. Y.; Oh, K. S.; Park, D.; Song, S. H.; Rieh, Jae-Sung; Hwang, S. W.

In: IEEE Electron Device Letters, Vol. 32, No. 9, 5944946, 01.09.2011, p. 1179-1181.

Research output: Contribution to journal › Article

Hong, BH, Cho, N, Lee, SJ, Yu, YS, Choi, L, Jung, YC, Cho, KH, Yeo, KH, Kim, DW, Jin, GY, Oh, KS, Park, D, Song, SH, Rieh, J-S & Hwang, SW 2011, 'Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors: Effect of interface trap charge', IEEE Electron Device Letters, vol. 32, no. 9, 5944946, pp. 1179-1181. https://doi.org/10.1109/LED.2011.2159473
Hong BH, Cho N, Lee SJ, Yu YS, Choi L, Jung YC et al. Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors: Effect of interface trap charge. IEEE Electron Device Letters. 2011 Sep 1;32(9):1179-1181. 5944946. https://doi.org/10.1109/LED.2011.2159473
Hong, B. H. ; Cho, N. ; Lee, S. J. ; Yu, Y. S. ; Choi, L. ; Jung, Y. C. ; Cho, K. H. ; Yeo, K. H. ; Kim, D. W. ; Jin, G. Y. ; Oh, K. S. ; Park, D. ; Song, S. H. ; Rieh, Jae-Sung ; Hwang, S. W. / Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors : Effect of interface trap charge. In: IEEE Electron Device Letters. 2011 ; Vol. 32, No. 9. pp. 1179-1181.
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