Subthreshold swing characteristics of nanowire tunneling FETs with variation in gate coverage and channel diameter

Minsuk Kim, Youngin Jeon, Yoonjoong Kim, Sangsig Kim

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼10<sup>13</sup>, and an on-current of ∼10<sup>-5</sup> A/μm.

Original languageEnglish
Pages (from-to)780-783
Number of pages4
JournalCurrent Applied Physics
Volume15
Issue number7
DOIs
Publication statusPublished - 2015 Apr 21

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Field effect transistors
Nanowires
nanowires
field effect transistors
Silicon
Drain current
silicon
simulation

Keywords

  • Gate coverage
  • Nanowire
  • Sub-60 mV/dec
  • Subthreshold swing (SS)
  • Tunneling field effect transistor (TFET)

ASJC Scopus subject areas

  • Materials Science(all)
  • Physics and Astronomy(all)

Cite this

Subthreshold swing characteristics of nanowire tunneling FETs with variation in gate coverage and channel diameter. / Kim, Minsuk; Jeon, Youngin; Kim, Yoonjoong; Kim, Sangsig.

In: Current Applied Physics, Vol. 15, No. 7, 21.04.2015, p. 780-783.

Research output: Contribution to journalArticle

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abstract = "In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30{\%} to 100{\%}. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100{\%} exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼1013, and an on-current of ∼10-5 A/μm.",
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N2 - In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼1013, and an on-current of ∼10-5 A/μm.

AB - In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼1013, and an on-current of ∼10-5 A/μm.

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