Suppression of edge effects based on analytic model for leakage current reduction of sub-40 nm DRAM device

Soo Han Choi, Young Hee Park, Chul Hong Park, Sang Hoon Lee, Moon Hyun Yoo, Jun Dong Cho, Gyu-Tae Kim

Research output: Contribution to journalArticle

Abstract

With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and I leakage fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.

Original languageEnglish
Pages (from-to)658-661
Number of pages4
JournalIEICE Transactions on Electronics
VolumeE93-C
Issue number5
DOIs
Publication statusPublished - 2010 May 10

Fingerprint

Dynamic random access storage
Leakage currents
VLSI circuits
Lithography
Transistors

Keywords

  • Analytic model
  • Drive current
  • Edge effects
  • Leakage current
  • OPC
  • Retargeting
  • Shaping gate channels

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Suppression of edge effects based on analytic model for leakage current reduction of sub-40 nm DRAM device. / Choi, Soo Han; Park, Young Hee; Park, Chul Hong; Lee, Sang Hoon; Yoo, Moon Hyun; Cho, Jun Dong; Kim, Gyu-Tae.

In: IEICE Transactions on Electronics, Vol. E93-C, No. 5, 10.05.2010, p. 658-661.

Research output: Contribution to journalArticle

Choi, Soo Han ; Park, Young Hee ; Park, Chul Hong ; Lee, Sang Hoon ; Yoo, Moon Hyun ; Cho, Jun Dong ; Kim, Gyu-Tae. / Suppression of edge effects based on analytic model for leakage current reduction of sub-40 nm DRAM device. In: IEICE Transactions on Electronics. 2010 ; Vol. E93-C, No. 5. pp. 658-661.
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