Swallow counterless DMP PLL

Taewoo Kim, Soonseob Lee, Gwangseog Choi, Soowon Kim, Taegeun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes a new simple architecture of digital dividing system in dual-modulus prescaler phase-locked loop for wireless communications. In this new architecture a swallow counter is not employed while the same total division ratio as in a conventional system can be obtained. This simple architecture shows advantages in reducing power consumption and gate-counts and is suitable for small die area and low power applications. The circuit is designed in a standard 0.35 um CMOS process.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages606-608
Number of pages3
ISBN (Print)0780357272, 9780780357273
DOIs
Publication statusPublished - 1999
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999 Oct 261999 Oct 27

Publication series

NameICVC 1999 - 6th International Conference on VLSI and CAD

Other

Other6th International Conference on VLSI and CAD, ICVC 1999
CountryKorea, Republic of
CitySeoul
Period99/10/2699/10/27

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Kim, T., Lee, S., Choi, G., Kim, S., & Kim, T. (1999). Swallow counterless DMP PLL. In ICVC 1999 - 6th International Conference on VLSI and CAD (pp. 606-608). [821013] (ICVC 1999 - 6th International Conference on VLSI and CAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICVC.1999.821013