Techniques for compiler-directed cache coherence

Lynn Choi, Hock Beng Lim, Pen Chung Yew

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

The concepts underlying compiler-directed cache coherence are explained, and various approaches to this strategy are surveyed. Compiler-directed coherence emphasizes the interaction between architectural features and compiler optimization, which affects a variety of system and compiler designers. Several techniques for compiler-directed cache coherence, such as CMU C.mmp and two-phase invalidation (TPI), were implemented on existing microprocessors without hardware support. Overall, the performance of the `off-chip' implementation is comparable to both `on-chip' TPI and full-map hardware directory (HW), suggesting that off-chip TPI using off-the-shelf microprocessors is a practical solution.

Original languageEnglish
Pages (from-to)23-34
Number of pages12
JournalIEEE Parallel and Distributed Technology
Volume4
Issue number4
DOIs
Publication statusPublished - 1996 Dec 1
Externally publishedYes

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ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering
  • Theoretical Computer Science

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