Techniques for compiler-directed cache coherence

Lynn Choi; Hock Beng Lim; Pen Chung Yew

doi:10.1109/88.544434

Techniques for compiler-directed cache coherence

Lynn Choi, Hock Beng Lim, Pen Chung Yew

Research output: Contribution to journal › Article

6 Citations (Scopus)

Abstract

The concepts underlying compiler-directed cache coherence are explained, and various approaches to this strategy are surveyed. Compiler-directed coherence emphasizes the interaction between architectural features and compiler optimization, which affects a variety of system and compiler designers. Several techniques for compiler-directed cache coherence, such as CMU C.mmp and two-phase invalidation (TPI), were implemented on existing microprocessors without hardware support. Overall, the performance of the `off-chip' implementation is comparable to both `on-chip' TPI and full-map hardware directory (HW), suggesting that off-chip TPI using off-the-shelf microprocessors is a practical solution.

Original language	English
Pages (from-to)	23-34
Number of pages	12
Journal	IEEE Parallel and Distributed Technology
Volume	4
Issue number	4
DOIs	https://doi.org/10.1109/88.544434
Publication status	Published - 1996 Dec 1
Externally published	Yes

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ASJC Scopus subject areas

Computational Theory and Mathematics
Electrical and Electronic Engineering
Theoretical Computer Science

Cite this

Choi, L., Lim, H. B., & Yew, P. C. (1996). Techniques for compiler-directed cache coherence. IEEE Parallel and Distributed Technology, 4(4), 23-34. https://doi.org/10.1109/88.544434

@article{b2066fe52a8442ff915aef00ccee6e45,

title = "Techniques for compiler-directed cache coherence",

abstract = "The concepts underlying compiler-directed cache coherence are explained, and various approaches to this strategy are surveyed. Compiler-directed coherence emphasizes the interaction between architectural features and compiler optimization, which affects a variety of system and compiler designers. Several techniques for compiler-directed cache coherence, such as CMU C.mmp and two-phase invalidation (TPI), were implemented on existing microprocessors without hardware support. Overall, the performance of the `off-chip' implementation is comparable to both `on-chip' TPI and full-map hardware directory (HW), suggesting that off-chip TPI using off-the-shelf microprocessors is a practical solution.",

author = "Lynn Choi and Lim, {Hock Beng} and Yew, {Pen Chung}",

year = "1996",

month = "12",

day = "1",

doi = "10.1109/88.544434",

language = "English",

volume = "4",

pages = "23--34",

journal = "IEEE Parallel and Distributed Technology",

issn = "1063-6552",

publisher = "IEEE Computer Society",

number = "4",

}

TY - JOUR

T1 - Techniques for compiler-directed cache coherence

AU - Choi, Lynn

AU - Lim, Hock Beng

AU - Yew, Pen Chung

PY - 1996/12/1

Y1 - 1996/12/1

N2 - The concepts underlying compiler-directed cache coherence are explained, and various approaches to this strategy are surveyed. Compiler-directed coherence emphasizes the interaction between architectural features and compiler optimization, which affects a variety of system and compiler designers. Several techniques for compiler-directed cache coherence, such as CMU C.mmp and two-phase invalidation (TPI), were implemented on existing microprocessors without hardware support. Overall, the performance of the `off-chip' implementation is comparable to both `on-chip' TPI and full-map hardware directory (HW), suggesting that off-chip TPI using off-the-shelf microprocessors is a practical solution.

AB - The concepts underlying compiler-directed cache coherence are explained, and various approaches to this strategy are surveyed. Compiler-directed coherence emphasizes the interaction between architectural features and compiler optimization, which affects a variety of system and compiler designers. Several techniques for compiler-directed cache coherence, such as CMU C.mmp and two-phase invalidation (TPI), were implemented on existing microprocessors without hardware support. Overall, the performance of the `off-chip' implementation is comparable to both `on-chip' TPI and full-map hardware directory (HW), suggesting that off-chip TPI using off-the-shelf microprocessors is a practical solution.

UR - http://www.scopus.com/inward/record.url?scp=0030415464&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030415464&partnerID=8YFLogxK

U2 - 10.1109/88.544434

DO - 10.1109/88.544434

M3 - Article

AN - SCOPUS:0030415464

VL - 4

SP - 23

EP - 34

JO - IEEE Parallel and Distributed Technology

JF - IEEE Parallel and Distributed Technology

SN - 1063-6552

IS - 4

ER -

Access to Document

10.1109/88.544434