The effect of device layout schemes on RF performance of multi-finger MOSFETs

Yongho Oh, Jae Sung Rieh

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-μm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (Cegs, Cegd) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (fT) and maximum oscillation frequency (fmax) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers Nf on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result, fT is slightly degraded but fmax is significantly improved, especially for larger Nf, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.

Original languageEnglish
Pages (from-to)785-791
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE95-C
Issue number5
DOIs
Publication statusPublished - 2012 May

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Keywords

  • FT
  • Fmax
  • Gate resistance
  • Layout
  • RF MOSFET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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