Since the introduction of silicon nanowire field-effect transistors (SiNW FETs) as a new technology for highly integrated circuits, their scaling behavior has been of crucial importance for the continuation of Moore's law. To date most studies have been of a theoretical nature, as small wire spacing is difficult to achieve experimentally. Here we successfully fabricated and investigated arrays of sub 20 nm SiNW FETs with wire spacing as small as 30 nm for the first time. The channels are contacted using global buried Si electrodes. Using the wafer as the back gate an investigation of the electrical performance of an array of SiNW FETs was undertaken. These experimental observations are supported by simulations using FlexPED.