Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors

Byeong Hyeon Lee, Jae Min Byun, Sangsig Kim, Sang Yeol Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.

Original languageEnglish
Title of host publicationAM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices
Subtitle of host publicationTFT Technologies and FPD Materials, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9784990875350
DOIs
Publication statusPublished - 2018 Aug 15
Event25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018 - Kyoto, Japan
Duration: 2018 Jul 32018 Jul 6

Other

Other25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018
CountryJapan
CityKyoto
Period18/7/318/7/6

Fingerprint

Thin film circuits
logic circuits
Logic circuits
Amorphous films
Thin film transistors
transistors
Metals
thin films
metals
Electric properties
Electrons

ASJC Scopus subject areas

  • Media Technology
  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics

Cite this

Lee, B. H., Byun, J. M., Kim, S., & Lee, S. Y. (2018). Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. In AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings [8437413] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/AM-FPD.2018.8437413

Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. / Lee, Byeong Hyeon; Byun, Jae Min; Kim, Sangsig; Lee, Sang Yeol.

AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8437413.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, BH, Byun, JM, Kim, S & Lee, SY 2018, Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. in AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings., 8437413, Institute of Electrical and Electronics Engineers Inc., 25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018, Kyoto, Japan, 18/7/3. https://doi.org/10.23919/AM-FPD.2018.8437413
Lee BH, Byun JM, Kim S, Lee SY. Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. In AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. 8437413 https://doi.org/10.23919/AM-FPD.2018.8437413
Lee, Byeong Hyeon ; Byun, Jae Min ; Kim, Sangsig ; Lee, Sang Yeol. / Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors. AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018.
@inproceedings{918b819aa0304d60b966480e4da36f00,
title = "Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors",
abstract = "Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.",
author = "Lee, {Byeong Hyeon} and Byun, {Jae Min} and Sangsig Kim and Lee, {Sang Yeol}",
year = "2018",
month = "8",
day = "15",
doi = "10.23919/AM-FPD.2018.8437413",
language = "English",
isbn = "9784990875350",
booktitle = "AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors

AU - Lee, Byeong Hyeon

AU - Byun, Jae Min

AU - Kim, Sangsig

AU - Lee, Sang Yeol

PY - 2018/8/15

Y1 - 2018/8/15

N2 - Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.

AB - Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.

UR - http://www.scopus.com/inward/record.url?scp=85053137064&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85053137064&partnerID=8YFLogxK

U2 - 10.23919/AM-FPD.2018.8437413

DO - 10.23919/AM-FPD.2018.8437413

M3 - Conference contribution

SN - 9784990875350

BT - AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices

PB - Institute of Electrical and Electronics Engineers Inc.

ER -