TY - GEN
T1 - Thin Film Logic Circuit with Metal Capping Layered amorphous SiZnSnO thin-film transistors
AU - Lee, Byeong Hyeon
AU - Byun, Jae Min
AU - Kim, Sangsig
AU - Lee, Sang Yeol
N1 - Funding Information:
This work was supported by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No.20172010104940). The Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2017R1D1A3B06033837).
Publisher Copyright:
© 2018 FTFMD.
PY - 2018/8/15
Y1 - 2018/8/15
N2 - Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.
AB - Various metal capping (MC) layer were deposited on the amorphous SiZnSnO channel layer to ensure high electrical properties. In addition, it was confirmed that the electrical characteristics change depending on the material of each MC layer. This effect is analyzed as a phenomenon which is caused by the difference between the work function of the MC layer and the work function of the channel layer. When the work function of the MC layer is smaller than the work function of the channel layer, the electrons are injected into the channel layer from the MC layer, so that higher electrical characteristics can be obtained. As a result, the electrical characteristics can be controlled by a simple change of the MC layer, and the logic circuits such as NOT, NAND, and NOR can be simply fabricated.
UR - http://www.scopus.com/inward/record.url?scp=85053137064&partnerID=8YFLogxK
U2 - 10.23919/AM-FPD.2018.8437413
DO - 10.23919/AM-FPD.2018.8437413
M3 - Conference contribution
AN - SCOPUS:85053137064
SN - 9784990875350
T3 - AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings
BT - AM-FPD 2018 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th International Workshop on Active-Matrix Flatpanel Displays and Devices - TFT Technologies and FPD Materials, AM-FPD 2018
Y2 - 3 July 2018 through 6 July 2018
ER -