Abstract
The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage (Vth) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced Vth in a FinFET with an S/D doping concentration (NS/D) of 5 × 1020 cm-3 is 9.277 mV. In order to suppress RDF-induced Vth variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an NS/D = 5 × 1019 cm-3) results in a standard deviation of 4.729 mV for RDF-induced Vth, while maintaining the on-state drive current (Ion) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to Vth variation with the adoption of the proposed M-I-S S/D structure.
| Original language | English |
|---|---|
| Pages (from-to) | 618-622 |
| Number of pages | 5 |
| Journal | Current Applied Physics |
| Volume | 16 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2016 Jun 1 |
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Keywords
- CMOS
- FinFET
- Metal-interlayer-semiconductor
- Random dopant fluctuation
- Variation
ASJC Scopus subject areas
- Materials Science(all)
- Physics and Astronomy(all)
Cite this
Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure. / Shin, Changho; Kim, Jeong Kyu; Shin, Changhwan; Kim, Jong-Kook; Yu, Hyun-Yong.
In: Current Applied Physics, Vol. 16, No. 6, 01.06.2016, p. 618-622.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure
AU - Shin, Changho
AU - Kim, Jeong Kyu
AU - Shin, Changhwan
AU - Kim, Jong-Kook
AU - Yu, Hyun-Yong
PY - 2016/6/1
Y1 - 2016/6/1
N2 - The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage (Vth) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced Vth in a FinFET with an S/D doping concentration (NS/D) of 5 × 1020 cm-3 is 9.277 mV. In order to suppress RDF-induced Vth variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an NS/D = 5 × 1019 cm-3) results in a standard deviation of 4.729 mV for RDF-induced Vth, while maintaining the on-state drive current (Ion) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to Vth variation with the adoption of the proposed M-I-S S/D structure.
AB - The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage (Vth) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced Vth in a FinFET with an S/D doping concentration (NS/D) of 5 × 1020 cm-3 is 9.277 mV. In order to suppress RDF-induced Vth variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an NS/D = 5 × 1019 cm-3) results in a standard deviation of 4.729 mV for RDF-induced Vth, while maintaining the on-state drive current (Ion) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to Vth variation with the adoption of the proposed M-I-S S/D structure.
KW - CMOS
KW - FinFET
KW - Metal-interlayer-semiconductor
KW - Random dopant fluctuation
KW - Variation
UR - http://www.scopus.com/inward/record.url?scp=84962227279&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962227279&partnerID=8YFLogxK
U2 - 10.1016/j.cap.2016.03.006
DO - 10.1016/j.cap.2016.03.006
M3 - Article
VL - 16
SP - 618
EP - 622
JO - Current Applied Physics
JF - Current Applied Physics
SN - 1567-1739
IS - 6
ER -