TornadoNoC: A lightweight and scalable on-Chip network architecture for the many-core era

Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Jongman Kim

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The rapid emergence of Chip Multi-Processors (CMP) as the de facto microprocessor archetype has highlighted the importance of scalable and efficient on-chip networks. Packet-based Networks-on-Chip (NoC) are gradually cementing themselves as the medium of choice for the multi-/many-core systems of the near future, due to their innate scalability. However, the prominence of the debilitating power wall requires the NoC to also be as energy efficient as possible. To achieve these two antipodal requirements-scalability and energy efficiency-we propose TornadoNoC, an interconnect architecture that employs a novel flow control mechanism. To prevent livelocks and deadlocks, a sequence numbering scheme and a dynamic ring inflation technique are proposed, and their correctness formally proven. The primary objective of TornadoNoC is to achieve substantial gains in (a) scalability to many-core systems and (b) the area/power footprint, as compared to current state-of-the-art router implementations. The new router is demonstrated to provide better scalability to hundreds of cores than an ideal single-cycle wormhole implementation and other scalability-enhanced low-cost routers. Extensive simulations using both synthetic traffic patterns and real applications running in a full-system simulator corroborate the efficacy of the proposed design. Finally, hardware synthesis analysis using commercial 65nm standard-cell libraries indicates that the area and power budgets of the new router are reduced by up to 53% and 58%, respectively, as compared to existing state-of-the-art low-cost routers.

Original languageEnglish
Article number56
JournalTransactions on Architecture and Code Optimization
Volume10
Issue number4
DOIs
Publication statusPublished - 2013 Dec 1
Externally publishedYes

Fingerprint

Network architecture
Routers
Scalability
Flow control
Energy efficiency
Microprocessor chips
Costs
Simulators
Hardware
Network-on-chip

Keywords

  • Deflection-based routing
  • Low-cost router architecture
  • Network-on-Chip
  • Ring-based interconnection network

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

Cite this

TornadoNoC : A lightweight and scalable on-Chip network architecture for the many-core era. / Lee, Junghee; Nicopoulos, Chrysostomos; Lee, Hyung Gyu; Kim, Jongman.

In: Transactions on Architecture and Code Optimization, Vol. 10, No. 4, 56, 01.12.2013.

Research output: Contribution to journalArticle

@article{8c060fee6e144388b8c53cf0a5311bfe,
title = "TornadoNoC: A lightweight and scalable on-Chip network architecture for the many-core era",
abstract = "The rapid emergence of Chip Multi-Processors (CMP) as the de facto microprocessor archetype has highlighted the importance of scalable and efficient on-chip networks. Packet-based Networks-on-Chip (NoC) are gradually cementing themselves as the medium of choice for the multi-/many-core systems of the near future, due to their innate scalability. However, the prominence of the debilitating power wall requires the NoC to also be as energy efficient as possible. To achieve these two antipodal requirements-scalability and energy efficiency-we propose TornadoNoC, an interconnect architecture that employs a novel flow control mechanism. To prevent livelocks and deadlocks, a sequence numbering scheme and a dynamic ring inflation technique are proposed, and their correctness formally proven. The primary objective of TornadoNoC is to achieve substantial gains in (a) scalability to many-core systems and (b) the area/power footprint, as compared to current state-of-the-art router implementations. The new router is demonstrated to provide better scalability to hundreds of cores than an ideal single-cycle wormhole implementation and other scalability-enhanced low-cost routers. Extensive simulations using both synthetic traffic patterns and real applications running in a full-system simulator corroborate the efficacy of the proposed design. Finally, hardware synthesis analysis using commercial 65nm standard-cell libraries indicates that the area and power budgets of the new router are reduced by up to 53{\%} and 58{\%}, respectively, as compared to existing state-of-the-art low-cost routers.",
keywords = "Deflection-based routing, Low-cost router architecture, Network-on-Chip, Ring-based interconnection network",
author = "Junghee Lee and Chrysostomos Nicopoulos and Lee, {Hyung Gyu} and Jongman Kim",
year = "2013",
month = "12",
day = "1",
doi = "10.1145/2555289.2555312",
language = "English",
volume = "10",
journal = "Transactions on Architecture and Code Optimization",
issn = "1544-3566",
publisher = "Association for Computing Machinery (ACM)",
number = "4",

}

TY - JOUR

T1 - TornadoNoC

T2 - A lightweight and scalable on-Chip network architecture for the many-core era

AU - Lee, Junghee

AU - Nicopoulos, Chrysostomos

AU - Lee, Hyung Gyu

AU - Kim, Jongman

PY - 2013/12/1

Y1 - 2013/12/1

N2 - The rapid emergence of Chip Multi-Processors (CMP) as the de facto microprocessor archetype has highlighted the importance of scalable and efficient on-chip networks. Packet-based Networks-on-Chip (NoC) are gradually cementing themselves as the medium of choice for the multi-/many-core systems of the near future, due to their innate scalability. However, the prominence of the debilitating power wall requires the NoC to also be as energy efficient as possible. To achieve these two antipodal requirements-scalability and energy efficiency-we propose TornadoNoC, an interconnect architecture that employs a novel flow control mechanism. To prevent livelocks and deadlocks, a sequence numbering scheme and a dynamic ring inflation technique are proposed, and their correctness formally proven. The primary objective of TornadoNoC is to achieve substantial gains in (a) scalability to many-core systems and (b) the area/power footprint, as compared to current state-of-the-art router implementations. The new router is demonstrated to provide better scalability to hundreds of cores than an ideal single-cycle wormhole implementation and other scalability-enhanced low-cost routers. Extensive simulations using both synthetic traffic patterns and real applications running in a full-system simulator corroborate the efficacy of the proposed design. Finally, hardware synthesis analysis using commercial 65nm standard-cell libraries indicates that the area and power budgets of the new router are reduced by up to 53% and 58%, respectively, as compared to existing state-of-the-art low-cost routers.

AB - The rapid emergence of Chip Multi-Processors (CMP) as the de facto microprocessor archetype has highlighted the importance of scalable and efficient on-chip networks. Packet-based Networks-on-Chip (NoC) are gradually cementing themselves as the medium of choice for the multi-/many-core systems of the near future, due to their innate scalability. However, the prominence of the debilitating power wall requires the NoC to also be as energy efficient as possible. To achieve these two antipodal requirements-scalability and energy efficiency-we propose TornadoNoC, an interconnect architecture that employs a novel flow control mechanism. To prevent livelocks and deadlocks, a sequence numbering scheme and a dynamic ring inflation technique are proposed, and their correctness formally proven. The primary objective of TornadoNoC is to achieve substantial gains in (a) scalability to many-core systems and (b) the area/power footprint, as compared to current state-of-the-art router implementations. The new router is demonstrated to provide better scalability to hundreds of cores than an ideal single-cycle wormhole implementation and other scalability-enhanced low-cost routers. Extensive simulations using both synthetic traffic patterns and real applications running in a full-system simulator corroborate the efficacy of the proposed design. Finally, hardware synthesis analysis using commercial 65nm standard-cell libraries indicates that the area and power budgets of the new router are reduced by up to 53% and 58%, respectively, as compared to existing state-of-the-art low-cost routers.

KW - Deflection-based routing

KW - Low-cost router architecture

KW - Network-on-Chip

KW - Ring-based interconnection network

UR - http://www.scopus.com/inward/record.url?scp=84892475005&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84892475005&partnerID=8YFLogxK

U2 - 10.1145/2555289.2555312

DO - 10.1145/2555289.2555312

M3 - Article

AN - SCOPUS:84892475005

VL - 10

JO - Transactions on Architecture and Code Optimization

JF - Transactions on Architecture and Code Optimization

SN - 1544-3566

IS - 4

M1 - 56

ER -