TornadoNoC: A Lightweight and Scalable On-Chip Network Architecture for the Many-Core Era

Junghee Lee, Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee

Research output: Contribution to journalArticle

Abstract

The rapid emergence of Chip Multi-Processors (CMP) as the de facto microprocessor archetype has highlighted the importance of scalable and efficient on-chip networks. Packet-based Networks-on-Chip (NoC) are gradually cementing themselves as the medium of choice for the multi-/many-core systems of the near future, due to their innate scalability. However, the prominence of the debilitating power wall requires the NoC to also be as energy efficient as possible. To achieve these two antipodal requirements'scalability and energy efficiency'we propose TornadoNoC, an interconnect architecture that employs a novel flow control mechanism. To prevent livelocks and deadlocks, a sequence numbering scheme and a dynamic ring inflation technique are proposed, and their correctness formally proven. The primary objective of TornadoNoC is to achieve substantial gains in (a) scalability to many-core systems and (b) the area/power footprint, as compared to current state-of-the-art router implementations. The new router is demonstrated to provide better scalability to hundreds of cores than an ideal single-cycle wormhole implementation and other scalabilityenhanced low-cost routers. Extensive simulations using both synthetic traffic patterns and real applications running in a full-system simulator corroborate the efficacy of the proposed design. Finally, hardware synthesis analysis using commercial 65nm standard-cell libraries indicates that the area and power budgets of the new router are reduced by up to 53% and 58%, respectively, as compared to existing state-of-the-art low-cost routers.

Original languageEnglish
Pages (from-to)1-30
Number of pages30
JournalACM Transactions on Architecture and Code Optimization
Volume10
Issue number4
DOIs
Publication statusPublished - 2013 Jan 1
Externally publishedYes

Keywords

  • Algorithms
  • Architecture
  • Deflection-Based Routing
  • Design
  • Low-Cost Router
  • Network-On-Chip
  • Performance
  • Ring-Based Interconnection Network

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

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