Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

Ikjun Cho, Beom Joon Kim, Sook Won Ryu, Jeong Ho Cho, Jinhan Cho

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-AuNPs) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-AuNP)n films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. For a single AuNP layer (i.e. PAD/TOA-AuNP)1) with a number density of 1.82 × 1012 cm-2, the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four AuNP layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔVth) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 106) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate.

Original languageEnglish
Article number505604
JournalNanotechnology
Volume25
Issue number50
DOIs
Publication statusPublished - 2014 Dec 19

Fingerprint

Metal Nanoparticles
Charge trapping
Metal nanoparticles
Transistors
Data storage equipment
Equipment and Supplies
Organic field effect transistors
Multilayers
Metals
Dendrimers
Hydrophobic and Hydrophilic Interactions
Nanoparticles
Adsorption
Amines
Flexible electronics
Costs and Cost Analysis
Gate dielectrics
Hydrophobicity
Adsorption isotherms

ASJC Scopus subject areas

  • Bioengineering
  • Chemistry(all)
  • Electrical and Electronic Engineering
  • Mechanical Engineering
  • Mechanics of Materials
  • Materials Science(all)

Cite this

Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array. / Cho, Ikjun; Kim, Beom Joon; Ryu, Sook Won; Cho, Jeong Ho; Cho, Jinhan.

In: Nanotechnology, Vol. 25, No. 50, 505604, 19.12.2014.

Research output: Contribution to journalArticle

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