Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors

Sola Woo; Jinsun Cho; Doohyeok Lim; Kyoungah Cho; Sangsig Kim

doi:10.1109/TED.2019.2939393

Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors

Sola Woo, Jinsun Cho, Doohyeok Lim, Kyoungah Cho, Sangsig Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the 2×2 SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system.

Original language	English
Article number	8836627
Pages (from-to)	4753-4758
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	11
DOIs	https://doi.org/10.1109/TED.2019.2939393
Publication status	Published - 2019 Nov

Keywords

Double-gate
feedback field-effect transistors (FBFETs)
static random access memory (SRAM)
synapse device
transposable memory

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2019.2939393

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title = "Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors",

abstract = "In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the 2×2 SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system.",

keywords = "Double-gate, feedback field-effect transistors (FBFETs), static random access memory (SRAM), synapse device, transposable memory",

author = "Sola Woo and Jinsun Cho and Doohyeok Lim and Kyoungah Cho and Sangsig Kim",

note = "Funding Information: Manuscript received July 26, 2019; accepted September 1, 2019. Date of publication September 13, 2019; date of current version October 29, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIP) under Grant NRF-2016R1E1A1A02920171, in part by the Ministry of Trade, Industry and Energy (MOTIE, Korea) through the Industrial Strategic Technology Development Program—Development of fabrication and device structure of feedback Si-channel 1T-SRAM for artificial intelligence—under Grant 10067791, and in part by the Brain Korea 21 Plus Project in 2019. The review of this article was arranged by Editor J. Kang. (Sola Woo and Jinsun Cho contributed equally to this work.) (Corresponding author: Sangsig Kim.) S. Woo, D. Lim, and K. Cho are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea.",

year = "2019",

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doi = "10.1109/TED.2019.2939393",

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pages = "4753--4758",

journal = "IEEE Transactions on Electron Devices",

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AU - Kim, Sangsig

N1 - Funding Information: Manuscript received July 26, 2019; accepted September 1, 2019. Date of publication September 13, 2019; date of current version October 29, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIP) under Grant NRF-2016R1E1A1A02920171, in part by the Ministry of Trade, Industry and Energy (MOTIE, Korea) through the Industrial Strategic Technology Development Program—Development of fabrication and device structure of feedback Si-channel 1T-SRAM for artificial intelligence—under Grant 10067791, and in part by the Brain Korea 21 Plus Project in 2019. The review of this article was arranged by Editor J. Kang. (Sola Woo and Jinsun Cho contributed equally to this work.) (Corresponding author: Sangsig Kim.) S. Woo, D. Lim, and K. Cho are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea.

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