Abstract
Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 x 760 μm² (PLL1) and 1300 x 840 μm² (PLL2) including probing pads.
| Original language | English |
|---|---|
| Journal | IEEE Transactions on Microwave Theory and Techniques |
| DOIs | |
| Publication status | Accepted/In press - 2016 Jul 7 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics
- Radiation
Cite this
Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology. / Kim, Namhyung; Song, Kiryong; Yun, Jongwon; Yoo, Junghwan; Rieh, Jae-Sung.
In: IEEE Transactions on Microwave Theory and Techniques, 07.07.2016.Research output: Contribution to journal › Article
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TY - JOUR
T1 - Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
AU - Kim, Namhyung
AU - Song, Kiryong
AU - Yun, Jongwon
AU - Yoo, Junghwan
AU - Rieh, Jae-Sung
PY - 2016/7/7
Y1 - 2016/7/7
N2 - Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 x 760 μm² (PLL1) and 1300 x 840 μm² (PLL2) including probing pads.
AB - Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 x 760 μm² (PLL1) and 1300 x 840 μm² (PLL2) including probing pads.
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U2 - 10.1109/TMTT.2016.2581816
DO - 10.1109/TMTT.2016.2581816
M3 - Article
AN - SCOPUS:84978955103
JO - IEEE Transactions on Microwave Theory and Techniques
JF - IEEE Transactions on Microwave Theory and Techniques
SN - 0018-9480
ER -