Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique

Chanyong Jeong, Young Jae Min, Soo Won Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This letter presents a new two-stage digital I/Q demodulator employing a reconfigurable 16-phase quadrature intermediate frequency (IF) sampling technique for multistandard wireless systems such as mobile TV applications. The proposed two-stage digital I/Q demodulator provides the flexibility for the multiphase scheme such as a quadrature phase shift keying (QPSK) and 16-quadrature amplitude modulation (QAM) at the level of down-mixing, which introduces an efficient architecture for the following decimation filter. In this letter, the prototype chip has been implemented in a 0.18μm standard CMOS technology and occupied with the active chip area of 0.02mm2. The power consumption of the fabricated chip is 0.42mW with a 1.8V supply voltage at the sampling frequency of 26 MHz. The experimental results show that the proposed two-stage digital I/Q demodulator is suitable for multistandard wireless systems which require small silicon area and low power dissipation.

Original languageEnglish
Pages (from-to)177-183
Number of pages7
Journalieice electronics express
Volume7
Issue number3
DOIs
Publication statusPublished - 2010 Feb 10

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Keywords

  • Demodulation
  • Down-mixing
  • Quadrature
  • Sigma-delta

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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