The importance of the thinning technology of silicon wafer is increasing in the MEMS packaging and the semiconductor packaging area. One of the packaging technique trying to do newly is 3D packaging with light weight and low cost. In this work, as ultra thin silicon substrate which has thickness of 50μm was used as capping substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through, ultra thin thickness (<5μm), hermetic sealing and low loss. Hence, it results in high increased density with reduced volume, and the interconnection dramatically shortened which can significantly improve the performance. The fabricated via hole size of front side was increased 10μm as 60μm and that of back side was reduced 10um as 40μm. The insertion loss of the packaged CPW was 0.54-0.67 dB.