Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO                         
                        2
                                                  with record-low leakage current

Tae In Lee; Hyun Jun Ahn; Min Ju Kim; Eui Joong Shin; Seung Hwan Lee; Sung Won Shin; Wan Sik Hwang; Hyun-Yong Yu; Byung Jin Cho

doi:10.1109/LED.2019.2899139

Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO ₂ with record-low leakage current

Tae In Lee, Hyun Jun Ahn, Min Ju Kim, Eui Joong Shin, Seung Hwan Lee, Sung Won Shin, Wan Sik Hwang, Hyun-Yong Yu, Byung Jin Cho

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

An advanced gate stack of Y-doped ZrO ₂ high-k dielectric is demonstrated for Ge MOSFETs. ZrO ₂ is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO ₂ to enhance interfacial properties. The gate stack of ZrO ₂ with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (D _it ) of 1.2 × 10 ¹² eV ^-1 cm ^-2 , a record-low gate leakage current of 1.14 × 10 ^-7 A/cm ² at -1V, and peak mobility of 68 cm ² / V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.

Original language	English
Article number	8641385
Pages (from-to)	502-505
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	4
DOIs	https://doi.org/10.1109/LED.2019.2899139
Publication status	Published - 2019 Apr 1

Keywords

EOT
gate leakage current
Germanium
interface properties
MOSFET

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2019.2899139

Fingerprint Dive into the research topics of 'Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO <sub>2</sub> with record-low leakage current'. Together they form a unique fingerprint.

Cite this

Lee, T. I., Ahn, H. J., Kim, M. J., Shin, E. J., Lee, S. H., Shin, S. W., Hwang, W. S., Yu, H-Y., & Cho, B. J. (2019). Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO ₂ with record-low leakage current IEEE Electron Device Letters, 40(4), 502-505. [8641385]. https://doi.org/10.1109/LED.2019.2899139

Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO ₂ with record-low leakage current . / Lee, Tae In; Ahn, Hyun Jun; Kim, Min Ju; Shin, Eui Joong; Lee, Seung Hwan; Shin, Sung Won; Hwang, Wan Sik; Yu, Hyun-Yong; Cho, Byung Jin.

In: IEEE Electron Device Letters, Vol. 40, No. 4, 8641385, 01.04.2019, p. 502-505.

Research output: Contribution to journal › Article › peer-review

Lee, TI, Ahn, HJ, Kim, MJ, Shin, EJ, Lee, SH, Shin, SW, Hwang, WS, Yu, H-Y & Cho, BJ 2019, ' Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO ₂ with record-low leakage current ', IEEE Electron Device Letters, vol. 40, no. 4, 8641385, pp. 502-505. https://doi.org/10.1109/LED.2019.2899139

Lee TI, Ahn HJ, Kim MJ, Shin EJ, Lee SH, Shin SW et al. Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO ₂ with record-low leakage current IEEE Electron Device Letters. 2019 Apr 1;40(4):502-505. 8641385. https://doi.org/10.1109/LED.2019.2899139

Lee, Tae In ; Ahn, Hyun Jun ; Kim, Min Ju ; Shin, Eui Joong ; Lee, Seung Hwan ; Shin, Sung Won ; Hwang, Wan Sik ; Yu, Hyun-Yong ; Cho, Byung Jin. / Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO ₂ with record-low leakage current In: IEEE Electron Device Letters. 2019 ; Vol. 40, No. 4. pp. 502-505.

@article{b4e0ca04d6d947fd923fa86ab6cc0795,

title = " Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO 2 with record-low leakage current ",

abstract = " An advanced gate stack of Y-doped ZrO 2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO 2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO 2 to enhance interfacial properties. The gate stack of ZrO 2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (D it ) of 1.2 × 10 12 eV -1 cm -2 , a record-low gate leakage current of 1.14 × 10 -7 A/cm 2 at -1V, and peak mobility of 68 cm 2 / V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs. ",

keywords = "EOT, gate leakage current, Germanium, interface properties, MOSFET",

author = "Lee, {Tae In} and Ahn, {Hyun Jun} and Kim, {Min Ju} and Shin, {Eui Joong} and Lee, {Seung Hwan} and Shin, {Sung Won} and Hwang, {Wan Sik} and Hyun-Yong Yu and Cho, {Byung Jin}",

year = "2019",

month = apr,

day = "1",

doi = "10.1109/LED.2019.2899139",

language = "English",

volume = "40",

pages = "502--505",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO 2 with record-low leakage current

AU - Lee, Tae In

AU - Ahn, Hyun Jun

AU - Kim, Min Ju

AU - Shin, Eui Joong

AU - Lee, Seung Hwan

AU - Shin, Sung Won

AU - Hwang, Wan Sik

AU - Yu, Hyun-Yong

AU - Cho, Byung Jin

PY - 2019/4/1

Y1 - 2019/4/1

N2 - An advanced gate stack of Y-doped ZrO 2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO 2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO 2 to enhance interfacial properties. The gate stack of ZrO 2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (D it ) of 1.2 × 10 12 eV -1 cm -2 , a record-low gate leakage current of 1.14 × 10 -7 A/cm 2 at -1V, and peak mobility of 68 cm 2 / V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.

AB - An advanced gate stack of Y-doped ZrO 2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO 2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO 2 to enhance interfacial properties. The gate stack of ZrO 2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (D it ) of 1.2 × 10 12 eV -1 cm -2 , a record-low gate leakage current of 1.14 × 10 -7 A/cm 2 at -1V, and peak mobility of 68 cm 2 / V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.

KW - EOT

KW - gate leakage current

KW - Germanium

KW - interface properties

KW - MOSFET

UR - http://www.scopus.com/inward/record.url?scp=85064071005&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85064071005&partnerID=8YFLogxK

U2 - 10.1109/LED.2019.2899139

DO - 10.1109/LED.2019.2899139

M3 - Article

AN - SCOPUS:85064071005

VL - 40

SP - 502

EP - 505

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 4

M1 - 8641385

ER -