Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO2 with record-low leakage current

Tae In Lee; Hyun Jun Ahn; Min Ju Kim; Eui Joong Shin; Seung Hwan Lee; Sung Won Shin; Wan Sik Hwang; Hyun Yong Yu; Byung Jin Cho

doi:10.1109/LED.2019.2899139

Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO₂ with record-low leakage current

Tae In Lee, Hyun Jun Ahn, Min Ju Kim, Eui Joong Shin, Seung Hwan Lee, Sung Won Shin, Wan Sik Hwang, Hyun Yong Yu, Byung Jin Cho

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

An advanced gate stack of Y-doped ZrO₂ high-k dielectric is demonstrated for Ge MOSFETs. ZrO₂ is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO₂ to enhance interfacial properties. The gate stack of ZrO₂ with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (D_it) of 1.2 × 10¹² eV^-1cm^-2, a record-low gate leakage current of 1.14 × 10^-7 A/cm² at -1V, and peak mobility of 68 cm²/ V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.

Original language	English
Article number	8641385
Pages (from-to)	502-505
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	4
DOIs	https://doi.org/10.1109/LED.2019.2899139
Publication status	Published - 2019 Apr

Keywords

EOT
Germanium
MOSFET
gate leakage current
interface properties

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO₂ with record-low leakage current. / Lee, Tae In; Ahn, Hyun Jun; Kim, Min Ju; Shin, Eui Joong; Lee, Seung Hwan; Shin, Sung Won; Hwang, Wan Sik; Yu, Hyun Yong; Cho, Byung Jin.

In: IEEE Electron Device Letters, Vol. 40, No. 4, 8641385, 04.2019, p. 502-505.

Research output: Contribution to journal › Article › peer-review

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title = "Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using y Doped ZrO2 with record-low leakage current",

abstract = "An advanced gate stack of Y-doped ZrO2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO2 to enhance interfacial properties. The gate stack of ZrO2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (Dit) of 1.2 × 1012 eV-1cm-2, a record-low gate leakage current of 1.14 × 10-7 A/cm2 at -1V, and peak mobility of 68 cm2/ V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.",

keywords = "EOT, Germanium, MOSFET, gate leakage current, interface properties",

author = "Lee, {Tae In} and Ahn, {Hyun Jun} and Kim, {Min Ju} and Shin, {Eui Joong} and Lee, {Seung Hwan} and Shin, {Sung Won} and Hwang, {Wan Sik} and Yu, {Hyun Yong} and Cho, {Byung Jin}",

note = "Funding Information: Manuscript received January 18, 2019; revised February 1, 2019; accepted February 2, 2019. Date of publication February 13, 2019; date of current version April 2, 2019. This work was supported by the Industrial Strategic Technology Development Program (10048594, Technology Development of Ge nMOS/pMOS FinFET for 10nm Technology Node) funded by the Ministry of Trade, Industry and Energy (MI, Korea). The review of this letter was arranged by Editor S. Hall. (Corresponding author: Byung Jin Cho.) T. I. Lee, H. J. Ahn, M. J. Kim, E. J. Shin, S. H. Lee, S. W. Shin, and B. J. Cho are with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, South Korea (e-mail: bjcho@kaist.edu). Publisher Copyright: {\textcopyright} 1980-2012 IEEE. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.",

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AU - Ahn, Hyun Jun

AU - Kim, Min Ju

AU - Shin, Eui Joong

AU - Lee, Seung Hwan

AU - Shin, Sung Won

AU - Hwang, Wan Sik

AU - Yu, Hyun Yong

AU - Cho, Byung Jin

N1 - Funding Information: Manuscript received January 18, 2019; revised February 1, 2019; accepted February 2, 2019. Date of publication February 13, 2019; date of current version April 2, 2019. This work was supported by the Industrial Strategic Technology Development Program (10048594, Technology Development of Ge nMOS/pMOS FinFET for 10nm Technology Node) funded by the Ministry of Trade, Industry and Energy (MI, Korea). The review of this letter was arranged by Editor S. Hall. (Corresponding author: Byung Jin Cho.) T. I. Lee, H. J. Ahn, M. J. Kim, E. J. Shin, S. H. Lee, S. W. Shin, and B. J. Cho are with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, South Korea (e-mail: bjcho@kaist.edu). Publisher Copyright: © 1980-2012 IEEE. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.

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N2 - An advanced gate stack of Y-doped ZrO2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO2 to enhance interfacial properties. The gate stack of ZrO2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (Dit) of 1.2 × 1012 eV-1cm-2, a record-low gate leakage current of 1.14 × 10-7 A/cm2 at -1V, and peak mobility of 68 cm2/ V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.

AB - An advanced gate stack of Y-doped ZrO2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO2 to enhance interfacial properties. The gate stack of ZrO2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (Dit) of 1.2 × 1012 eV-1cm-2, a record-low gate leakage current of 1.14 × 10-7 A/cm2 at -1V, and peak mobility of 68 cm2/ V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.

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KW - interface properties

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