An advanced gate stack of Y-doped ZrO 2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO 2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO 2 to enhance interfacial properties. The gate stack of ZrO 2 with 24% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density (D it ) of 1.2 × 10 12 eV -1 cm -2 , a record-low gate leakage current of 1.14 × 10 -7 A/cm 2 at -1V, and peak mobility of 68 cm 2 / V·s. The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.
- gate leakage current
- interface properties
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering