Unbiased Finite-Memory Digital Phase-Locked Loop

Sung Hyun You, Jung Min Pak, Choon Ki Ahn, Peng Shi, Myo Taeg Lim

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.

Original languageEnglish
Article number7410011
Pages (from-to)798-802
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume63
Issue number8
DOIs
Publication statusPublished - 2016 Aug 1

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Phase locked loops
Data storage equipment
Computer simulation

Keywords

  • Digital phase-locked loop (DPLL)
  • finite-memory structure
  • unbiasedness

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Unbiased Finite-Memory Digital Phase-Locked Loop. / You, Sung Hyun; Pak, Jung Min; Ahn, Choon Ki; Shi, Peng; Lim, Myo Taeg.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 8, 7410011, 01.08.2016, p. 798-802.

Research output: Contribution to journalArticle

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