Utilization of the on-chip L2 cache area in CC-NUMA multiprocessors for applications with a small working set

Sung Woo Chung, Hyong Shik Kim, Chu Shik Jhon

Research output: Contribution to journalArticle

Abstract

In CC-NUMA multiprocessor systems, it is important to reduce the remote memory access time. Based upon the fact that increasing the size of the LRU second-level (L2) cache more than a certain value does not reduce the cache miss rate significantly, in this paper, we propose two split L2 caches to utilize the surplus of the L2 cache. The split L2 caches are composed of a traditional LRU cache and another cache to reduce the remote memory access time. Both work together to reduce total L2 cache miss time by keeping remote (or long-distance) blocks as well as recently used blocks. For another cache, we propose two alternatives: an L2-RVC (Level 2 - Remote Victim Cache) and an L2-DAVC (Level 2 Distance-Aware Victim Cache). The proposed split L2 caches reduce total execution time by up to 27%. It is also found that the proposed split L2 caches outperform the traditional single LRU cache of double size.

Original languageEnglish
Pages (from-to)1617-1624
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE87-D
Issue number7
Publication statusPublished - 2004 Jul
Externally publishedYes

Keywords

  • CC-NUMA multiprocessor
  • Cache replacement policy
  • Distance-aware cache
  • Interconnection network
  • On-chip cache
  • Remote victim cache

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Fingerprint Dive into the research topics of 'Utilization of the on-chip L2 cache area in CC-NUMA multiprocessors for applications with a small working set'. Together they form a unique fingerprint.

  • Cite this