TY - JOUR
T1 - Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al 2 O 3 /Si 3 N 4 /SiO 2 /poly-Si capacitors
AU - Hong, Suk Bum
AU - Park, Ju Hyun
AU - Lee, Tae Ho
AU - Lim, Jun Hee
AU - Shin, Changhwan
AU - Park, Young Woo
AU - Kim, Tae Geun
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (No. 2016R1A3B1908249), This work was also supported by Korea University Future Research Grant, and Samsung Semiconductor Research Center in Korea University. The authors would also like to thank Eugene Technology incorporation for the supply of poly-Si channel wafers.
Publisher Copyright:
© 2017 Elsevier B.V.
Copyright:
Copyright 2019 Elsevier B.V., All rights reserved.
PY - 2019/5/31
Y1 - 2019/5/31
N2 - This study presents the improved memory properties of TiN/Al 2 O 3 /Si 3 N 4 /SiO 2 /poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H 2 and D 2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO 2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.
AB - This study presents the improved memory properties of TiN/Al 2 O 3 /Si 3 N 4 /SiO 2 /poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H 2 and D 2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO 2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.
KW - Grain boundary
KW - Interface trap
KW - Poly-silicon channel
KW - Rapid thermal annealing
KW - TANOS
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U2 - 10.1016/j.apsusc.2017.11.226
DO - 10.1016/j.apsusc.2017.11.226
M3 - Article
AN - SCOPUS:85036529770
VL - 477
SP - 104
EP - 110
JO - Applied Surface Science
JF - Applied Surface Science
SN - 0169-4332
ER -