Vertical arrays of copper nanotube grown on silicon substrate by CMOS compatible electrochemical process for IC packaging applications

Daniel Choi, Viola Fucsko, E. H. Yang, Jung Rae Park, Fahad Khalid, Young Kun Kim

Research output: Contribution to journalArticle

Abstract

We present an eiectrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m·K compared to the 0.24 W/m·K from Cu bulk materials, which shows an enhancement of about 146% as a result of the more efficient thermal conduction in Cu nanotubes.

Original languageEnglish
Pages (from-to)154-157
Number of pages4
JournalJournal of Microelectronics and Electronic Packaging
Volume6
Issue number3
DOIs
Publication statusPublished - 2009

Keywords

  • Copper nanotubes
  • Electrodeposition
  • Packaging
  • Thermal conductivity

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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