Vertical arrays of copper nanotube grown on silicon substrate by CMOS compatible electrochemical process for IC packaging applications

Daniel Choi, Viola Fucsko, E. H. Yang, Jung Rae Park, Fahad Khalid, Young-geun Kim

Research output: Contribution to journalArticle

Abstract

We present an eiectrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m·K compared to the 0.24 W/m·K from Cu bulk materials, which shows an enhancement of about 146% as a result of the more efficient thermal conduction in Cu nanotubes.

Original languageEnglish
Pages (from-to)154-157
Number of pages4
JournalJournal of Microelectronics and Electronic Packaging
Volume6
Issue number3
Publication statusPublished - 2009

Fingerprint

Silicon
Nanotubes
Integrated circuits
Copper
Packaging
Metals
Substrates
Thermal conductivity
Nanopores
Aluminum Oxide
Oxide semiconductors
Nanowires
Alumina
Heat transfer
Fabrication

Keywords

  • Copper nanotubes
  • Electrodeposition
  • Packaging
  • Thermal conductivity

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Vertical arrays of copper nanotube grown on silicon substrate by CMOS compatible electrochemical process for IC packaging applications. / Choi, Daniel; Fucsko, Viola; Yang, E. H.; Park, Jung Rae; Khalid, Fahad; Kim, Young-geun.

In: Journal of Microelectronics and Electronic Packaging, Vol. 6, No. 3, 2009, p. 154-157.

Research output: Contribution to journalArticle

@article{97033dc690064358bb0336becb56ad90,
title = "Vertical arrays of copper nanotube grown on silicon substrate by CMOS compatible electrochemical process for IC packaging applications",
abstract = "We present an eiectrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m·K compared to the 0.24 W/m·K from Cu bulk materials, which shows an enhancement of about 146{\%} as a result of the more efficient thermal conduction in Cu nanotubes.",
keywords = "Copper nanotubes, Electrodeposition, Packaging, Thermal conductivity",
author = "Daniel Choi and Viola Fucsko and Yang, {E. H.} and Park, {Jung Rae} and Fahad Khalid and Young-geun Kim",
year = "2009",
language = "English",
volume = "6",
pages = "154--157",
journal = "The International journal for hybrid microelectronics",
issn = "1551-4897",
publisher = "IMAPS-International Microelectronics and Packaging Society",
number = "3",

}

TY - JOUR

T1 - Vertical arrays of copper nanotube grown on silicon substrate by CMOS compatible electrochemical process for IC packaging applications

AU - Choi, Daniel

AU - Fucsko, Viola

AU - Yang, E. H.

AU - Park, Jung Rae

AU - Khalid, Fahad

AU - Kim, Young-geun

PY - 2009

Y1 - 2009

N2 - We present an eiectrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m·K compared to the 0.24 W/m·K from Cu bulk materials, which shows an enhancement of about 146% as a result of the more efficient thermal conduction in Cu nanotubes.

AB - We present an eiectrodeposition-based fabrication process which can be complementary metal oxide semiconductor (CMOS) compatible for creating vertical arrays of copper (Cu) nanotubes for integrated circuit (IC) packaging applications. Since such nanotube structures offer high surface-to-volume ratios, low resistivity, and high thermal conductivity, they are especially suited for IC packaging applications requiring efficient heat transfer as well as electrical interconnect applications. In this work, Cu nanotube arrays were electrodeposited into alumina nanopore templates with pore diameters of approximately 50 nm and 100 nm. Simulation and measurements of the vertical arrays of Cu nanotubes showed greatly enhanced thermal conductivity in the direction of nanotube alignment compared with Cu nanowires and bulk Cu. The thermal conductivity of the vertical arrays of Cu nanotubes at 100°C is about 0.35W/m·K compared to the 0.24 W/m·K from Cu bulk materials, which shows an enhancement of about 146% as a result of the more efficient thermal conduction in Cu nanotubes.

KW - Copper nanotubes

KW - Electrodeposition

KW - Packaging

KW - Thermal conductivity

UR - http://www.scopus.com/inward/record.url?scp=84890611521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84890611521&partnerID=8YFLogxK

M3 - Article

VL - 6

SP - 154

EP - 157

JO - The International journal for hybrid microelectronics

JF - The International journal for hybrid microelectronics

SN - 1551-4897

IS - 3

ER -