TY - JOUR
T1 - Vertical NOR-logic circuits constructed using nanoparticle films on plastic substrates
AU - Choi, Jinyong
AU - Yun, Junggwon
AU - Cho, Kyoungah
AU - Kim, Sangsig
PY - 2014/8
Y1 - 2014/8
N2 - In this study, a NOR-logic circuit is constructed by the vertical stacking of three individual thin-film transistors (TFTs) with the channels of solutionprocessed chalcogenide nanoparticle (NP) films on a plastic substrate. The NOR-logic circuit consists of two p-type HgTe NP-based TFTs, which act as drivers, and one n-type HgSe NP-based TFT, which plays the role of an active load. The logic operation is observed with a substantial difference in V out between the logic state of "00" and the other logic states, and the logic swing is >60%.
AB - In this study, a NOR-logic circuit is constructed by the vertical stacking of three individual thin-film transistors (TFTs) with the channels of solutionprocessed chalcogenide nanoparticle (NP) films on a plastic substrate. The NOR-logic circuit consists of two p-type HgTe NP-based TFTs, which act as drivers, and one n-type HgSe NP-based TFT, which plays the role of an active load. The logic operation is observed with a substantial difference in V out between the logic state of "00" and the other logic states, and the logic swing is >60%.
UR - http://www.scopus.com/inward/record.url?scp=84906064996&partnerID=8YFLogxK
U2 - 10.7567/JJAP.53.08NE02
DO - 10.7567/JJAP.53.08NE02
M3 - Article
AN - SCOPUS:84906064996
VL - 53
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 8 SPEC. ISSUE 3
M1 - 08NE02
ER -