VL-ECC: Variable data-length error correction code for embedded memory in DSP applications

Jangwon Park, Jongsun Park, Swarup Bhunia

Research output: Contribution to journalArticle

14 Citations (Scopus)

Abstract

Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word. They suffer from either adequate protection against multibit failures or large overhead due to encoding/decoding logic and parity bits. To address this issue, we present a variable data-length ECC (VL-ECC) for the embedded memory devices of digital signal processors, in which the data length of ECC can be dynamically reconfigured to preferentially protect the relatively more important bits. In the proposed VL-ECC, when the number of failures exceeds the error correction capability, the data length of ECC is reduced to focus on the relatively more important higher order data bit parts, thereby minimizing system quality degradation due to bit failures. When the proposed VL-ECC is applied to the embedded memory devices of an H.264 processor, average peak signal-to-noise-ratio improvements of up to 5.12 dB are achieved compared with the conventional ECC under supply voltage of 800 mV or lower. With the fast Fourier transform processor, signal-to-quantization noise ratio is improved by up to 5.2 dB.

Original languageEnglish
Article number6677546
Pages (from-to)120-124
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume61
Issue number2
DOIs
Publication statusPublished - 2014 Jan 1

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Error correction
Data storage equipment
Digital signal processors
Electric potential
Fast Fourier transforms
Decoding
Signal to noise ratio
Degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

VL-ECC : Variable data-length error correction code for embedded memory in DSP applications. / Park, Jangwon; Park, Jongsun; Bhunia, Swarup.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 2, 6677546, 01.01.2014, p. 120-124.

Research output: Contribution to journalArticle

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