VLSI architecture for fast motion estimation based on bit-plane matching

Young Ki Ko, Sung-Jea Ko, Jong Wook Lee, Hyun Gyu Kim, Hyeong Cheol Oh

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, we propose a VLSI (very large scale integrated circuit) architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation by using a 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using only simple Boolean functions, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By controlling the data flow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and can exploit lower-cost fabrication technology. The proposed system was designed to process reference blocks of size 16 × 16 and the search range of [-16, 15]. We modeled and tested the proposed motion estimator in VHDL (very high speed integrated circuit hardware description language) and then synthesized the whole system which has been integrated in a 0.6-μm triple-metal CMOS chip of size 8.15 × 10.84 mm2.

Original languageEnglish
Pages (from-to)938-944
Number of pages7
JournalJournal of the Korean Physical Society
Volume37
Issue number6
Publication statusPublished - 2000 Dec 1

Fingerprint

integrated circuits
hardware description languages
estimators
VHSIC (circuits)
Boolean functions
shift registers
CMOS
hardware
chips
costs
fabrication
metals

ASJC Scopus subject areas

  • Physics and Astronomy(all)

Cite this

VLSI architecture for fast motion estimation based on bit-plane matching. / Ko, Young Ki; Ko, Sung-Jea; Lee, Jong Wook; Kim, Hyun Gyu; Oh, Hyeong Cheol.

In: Journal of the Korean Physical Society, Vol. 37, No. 6, 01.12.2000, p. 938-944.

Research output: Contribution to journalArticle

Ko, Young Ki ; Ko, Sung-Jea ; Lee, Jong Wook ; Kim, Hyun Gyu ; Oh, Hyeong Cheol. / VLSI architecture for fast motion estimation based on bit-plane matching. In: Journal of the Korean Physical Society. 2000 ; Vol. 37, No. 6. pp. 938-944.
@article{c156e7577dc745eba44e62af0ca8b62d,
title = "VLSI architecture for fast motion estimation based on bit-plane matching",
abstract = "In this paper, we propose a VLSI (very large scale integrated circuit) architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation by using a 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using only simple Boolean functions, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By controlling the data flow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and can exploit lower-cost fabrication technology. The proposed system was designed to process reference blocks of size 16 × 16 and the search range of [-16, 15]. We modeled and tested the proposed motion estimator in VHDL (very high speed integrated circuit hardware description language) and then synthesized the whole system which has been integrated in a 0.6-μm triple-metal CMOS chip of size 8.15 × 10.84 mm2.",
author = "Ko, {Young Ki} and Sung-Jea Ko and Lee, {Jong Wook} and Kim, {Hyun Gyu} and Oh, {Hyeong Cheol}",
year = "2000",
month = "12",
day = "1",
language = "English",
volume = "37",
pages = "938--944",
journal = "Journal of the Korean Physical Society",
issn = "0374-4884",
publisher = "Korean Physical Society",
number = "6",

}

TY - JOUR

T1 - VLSI architecture for fast motion estimation based on bit-plane matching

AU - Ko, Young Ki

AU - Ko, Sung-Jea

AU - Lee, Jong Wook

AU - Kim, Hyun Gyu

AU - Oh, Hyeong Cheol

PY - 2000/12/1

Y1 - 2000/12/1

N2 - In this paper, we propose a VLSI (very large scale integrated circuit) architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation by using a 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using only simple Boolean functions, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By controlling the data flow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and can exploit lower-cost fabrication technology. The proposed system was designed to process reference blocks of size 16 × 16 and the search range of [-16, 15]. We modeled and tested the proposed motion estimator in VHDL (very high speed integrated circuit hardware description language) and then synthesized the whole system which has been integrated in a 0.6-μm triple-metal CMOS chip of size 8.15 × 10.84 mm2.

AB - In this paper, we propose a VLSI (very large scale integrated circuit) architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation by using a 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using only simple Boolean functions, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By controlling the data flow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and can exploit lower-cost fabrication technology. The proposed system was designed to process reference blocks of size 16 × 16 and the search range of [-16, 15]. We modeled and tested the proposed motion estimator in VHDL (very high speed integrated circuit hardware description language) and then synthesized the whole system which has been integrated in a 0.6-μm triple-metal CMOS chip of size 8.15 × 10.84 mm2.

UR - http://www.scopus.com/inward/record.url?scp=0034347673&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034347673&partnerID=8YFLogxK

M3 - Article

VL - 37

SP - 938

EP - 944

JO - Journal of the Korean Physical Society

JF - Journal of the Korean Physical Society

SN - 0374-4884

IS - 6

ER -