Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress

Jae-Sung Rieh, K. Watson, F. Guarin, Z. Yang, P. C. Wang, A. Joseph, G. Freeman, S. Subbanna

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress up to as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interracial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10 6 hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.

Original languageEnglish
Title of host publicationAnnual Proceedings - Reliability Physics (Symposium)
Pages184-188
Number of pages5
Publication statusPublished - 2002
Externally publishedYes
EventProceedings of the 2002 40th annual IEEE International Relaibility Physics Symposium Proceedings - Dallas, TX, United States
Duration: 2002 Apr 72002 Apr 11

Other

OtherProceedings of the 2002 40th annual IEEE International Relaibility Physics Symposium Proceedings
CountryUnited States
CityDallas, TX
Period02/4/702/4/11

Fingerprint

Heterojunction bipolar transistors
Reliability analysis
Degradation
Polysilicon
Bipolar transistors
Temperature
Single crystals
Heating

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Rieh, J-S., Watson, K., Guarin, F., Yang, Z., Wang, P. C., Joseph, A., ... Subbanna, S. (2002). Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress. In Annual Proceedings - Reliability Physics (Symposium) (pp. 184-188)

Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress. / Rieh, Jae-Sung; Watson, K.; Guarin, F.; Yang, Z.; Wang, P. C.; Joseph, A.; Freeman, G.; Subbanna, S.

Annual Proceedings - Reliability Physics (Symposium). 2002. p. 184-188.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rieh, J-S, Watson, K, Guarin, F, Yang, Z, Wang, PC, Joseph, A, Freeman, G & Subbanna, S 2002, Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress. in Annual Proceedings - Reliability Physics (Symposium). pp. 184-188, Proceedings of the 2002 40th annual IEEE International Relaibility Physics Symposium Proceedings, Dallas, TX, United States, 02/4/7.
Rieh J-S, Watson K, Guarin F, Yang Z, Wang PC, Joseph A et al. Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress. In Annual Proceedings - Reliability Physics (Symposium). 2002. p. 184-188
Rieh, Jae-Sung ; Watson, K. ; Guarin, F. ; Yang, Z. ; Wang, P. C. ; Joseph, A. ; Freeman, G. ; Subbanna, S. / Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress. Annual Proceedings - Reliability Physics (Symposium). 2002. pp. 184-188
@inproceedings{fca287d69a2648088bc0fd8011f1b54c,
title = "Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress",
abstract = "A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress up to as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interracial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10 6 hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.",
author = "Jae-Sung Rieh and K. Watson and F. Guarin and Z. Yang and Wang, {P. C.} and A. Joseph and G. Freeman and S. Subbanna",
year = "2002",
language = "English",
pages = "184--188",
booktitle = "Annual Proceedings - Reliability Physics (Symposium)",

}

TY - GEN

T1 - Wafer level forward current reliability analysis of 120 GHz production SiGe HBTs under accelerated current stress

AU - Rieh, Jae-Sung

AU - Watson, K.

AU - Guarin, F.

AU - Yang, Z.

AU - Wang, P. C.

AU - Joseph, A.

AU - Freeman, G.

AU - Subbanna, S.

PY - 2002

Y1 - 2002

N2 - A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress up to as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interracial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10 6 hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.

AB - A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress up to as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interracial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10 6 hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.

UR - http://www.scopus.com/inward/record.url?scp=0036088087&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036088087&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0036088087

SP - 184

EP - 188

BT - Annual Proceedings - Reliability Physics (Symposium)

ER -