Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress

Jae-Sung Rieh, K. Watson, F. Guarin, Z. Yang, P. C. Wang, A. Joseph, G. Freeman, S. Subbanna

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz fT and 100 GHz fmax. Accelerated current stress up to as high as JC=34 mA/μm2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interfacial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 106 hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.

Original languageEnglish
Title of host publicationIEEE International Reliability Physics Symposium Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages184-188
Number of pages5
Volume2002-January
ISBN (Print)0780373529
DOIs
Publication statusPublished - 2002
Externally publishedYes
Event40th Annual IEEE International Reliability Physics Symposium, IRPS 2002 - Dallas, United States
Duration: 2002 Apr 72002 Apr 11

Other

Other40th Annual IEEE International Reliability Physics Symposium, IRPS 2002
CountryUnited States
CityDallas
Period02/4/702/4/11

Fingerprint

Heterojunction bipolar transistors
Reliability analysis
Degradation
Polysilicon
Bipolar transistors
Temperature
Single crystals
Heating

Keywords

  • Acceleration
  • Bipolar transistors
  • Degradation
  • Germanium silicon alloys
  • Mechanical factors
  • Production
  • Robustness
  • Silicon germanium
  • Stress
  • Temperature

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Rieh, J-S., Watson, K., Guarin, F., Yang, Z., Wang, P. C., Joseph, A., ... Subbanna, S. (2002). Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress. In IEEE International Reliability Physics Symposium Proceedings (Vol. 2002-January, pp. 184-188). [996633] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RELPHY.2002.996633

Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress. / Rieh, Jae-Sung; Watson, K.; Guarin, F.; Yang, Z.; Wang, P. C.; Joseph, A.; Freeman, G.; Subbanna, S.

IEEE International Reliability Physics Symposium Proceedings. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 184-188 996633.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rieh, J-S, Watson, K, Guarin, F, Yang, Z, Wang, PC, Joseph, A, Freeman, G & Subbanna, S 2002, Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress. in IEEE International Reliability Physics Symposium Proceedings. vol. 2002-January, 996633, Institute of Electrical and Electronics Engineers Inc., pp. 184-188, 40th Annual IEEE International Reliability Physics Symposium, IRPS 2002, Dallas, United States, 02/4/7. https://doi.org/10.1109/RELPHY.2002.996633
Rieh J-S, Watson K, Guarin F, Yang Z, Wang PC, Joseph A et al. Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress. In IEEE International Reliability Physics Symposium Proceedings. Vol. 2002-January. Institute of Electrical and Electronics Engineers Inc. 2002. p. 184-188. 996633 https://doi.org/10.1109/RELPHY.2002.996633
Rieh, Jae-Sung ; Watson, K. ; Guarin, F. ; Yang, Z. ; Wang, P. C. ; Joseph, A. ; Freeman, G. ; Subbanna, S. / Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress. IEEE International Reliability Physics Symposium Proceedings. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. pp. 184-188
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AB - A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz fT and 100 GHz fmax. Accelerated current stress up to as high as JC=34 mA/μm2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interfacial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 106 hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.

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