Wafer level reliability evaluation of 120GHz SiGe HBT's

F. Guarin, Jae-Sung Rieh, Z. Yang, P. Wang, A. Joseph, G. Freeman, S. Subbanna

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a Wafer Level Reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. This technique was used to characterize the evolution of parametric shifts under current and temperature acceleration. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. A comparison of the WLR technique for Heterojunction Bipolar Transistors (HBT) implemented in SiGe and III-V material systems is also provided. Through comparison with long term stress results performed on packaged transistors, we have verified their consistency with wafer level stressing, thus providing a viable WLR methodology for lifetime verification in a relatively short stress time and moderate temperature.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS
Pages71-76
Number of pages6
Publication statusPublished - 2004
Externally publishedYes
Event5th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS - , Dominican Republic
Duration: 2004 Nov 32004 Nov 5

Other

Other5th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS
CountryDominican Republic
Period04/11/304/11/5

Fingerprint

Heterojunction bipolar transistors
Degradation
Temperature
Bipolar transistors
Polysilicon
Transistors
Heating

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Guarin, F., Rieh, J-S., Yang, Z., Wang, P., Joseph, A., Freeman, G., & Subbanna, S. (2004). Wafer level reliability evaluation of 120GHz SiGe HBT's. In Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS (pp. 71-76)

Wafer level reliability evaluation of 120GHz SiGe HBT's. / Guarin, F.; Rieh, Jae-Sung; Yang, Z.; Wang, P.; Joseph, A.; Freeman, G.; Subbanna, S.

Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS. 2004. p. 71-76.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Guarin, F, Rieh, J-S, Yang, Z, Wang, P, Joseph, A, Freeman, G & Subbanna, S 2004, Wafer level reliability evaluation of 120GHz SiGe HBT's. in Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS. pp. 71-76, 5th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS, Dominican Republic, 04/11/3.
Guarin F, Rieh J-S, Yang Z, Wang P, Joseph A, Freeman G et al. Wafer level reliability evaluation of 120GHz SiGe HBT's. In Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS. 2004. p. 71-76
Guarin, F. ; Rieh, Jae-Sung ; Yang, Z. ; Wang, P. ; Joseph, A. ; Freeman, G. ; Subbanna, S. / Wafer level reliability evaluation of 120GHz SiGe HBT's. Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS. 2004. pp. 71-76
@inproceedings{54e5ca332acc4293978ee3766c5d9526,
title = "Wafer level reliability evaluation of 120GHz SiGe HBT's",
abstract = "A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a Wafer Level Reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. This technique was used to characterize the evolution of parametric shifts under current and temperature acceleration. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. A comparison of the WLR technique for Heterojunction Bipolar Transistors (HBT) implemented in SiGe and III-V material systems is also provided. Through comparison with long term stress results performed on packaged transistors, we have verified their consistency with wafer level stressing, thus providing a viable WLR methodology for lifetime verification in a relatively short stress time and moderate temperature.",
author = "F. Guarin and Jae-Sung Rieh and Z. Yang and P. Wang and A. Joseph and G. Freeman and S. Subbanna",
year = "2004",
language = "English",
pages = "71--76",
booktitle = "Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS",

}

TY - GEN

T1 - Wafer level reliability evaluation of 120GHz SiGe HBT's

AU - Guarin, F.

AU - Rieh, Jae-Sung

AU - Yang, Z.

AU - Wang, P.

AU - Joseph, A.

AU - Freeman, G.

AU - Subbanna, S.

PY - 2004

Y1 - 2004

N2 - A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a Wafer Level Reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. This technique was used to characterize the evolution of parametric shifts under current and temperature acceleration. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. A comparison of the WLR technique for Heterojunction Bipolar Transistors (HBT) implemented in SiGe and III-V material systems is also provided. Through comparison with long term stress results performed on packaged transistors, we have verified their consistency with wafer level stressing, thus providing a viable WLR methodology for lifetime verification in a relatively short stress time and moderate temperature.

AB - A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a Wafer Level Reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. This technique was used to characterize the evolution of parametric shifts under current and temperature acceleration. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. A comparison of the WLR technique for Heterojunction Bipolar Transistors (HBT) implemented in SiGe and III-V material systems is also provided. Through comparison with long term stress results performed on packaged transistors, we have verified their consistency with wafer level stressing, thus providing a viable WLR methodology for lifetime verification in a relatively short stress time and moderate temperature.

UR - http://www.scopus.com/inward/record.url?scp=28444438792&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=28444438792&partnerID=8YFLogxK

M3 - Conference contribution

SP - 71

EP - 76

BT - Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS

ER -