A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a Wafer Level Reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f T and 100 GHz f max. Accelerated current stress as high as J C=34 mA/μm 2 was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. This technique was used to characterize the evolution of parametric shifts under current and temperature acceleration. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. A comparison of the WLR technique for Heterojunction Bipolar Transistors (HBT) implemented in SiGe and III-V material systems is also provided. Through comparison with long term stress results performed on packaged transistors, we have verified their consistency with wafer level stressing, thus providing a viable WLR methodology for lifetime verification in a relatively short stress time and moderate temperature.
|Number of pages||6|
|Journal||Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS|
|Publication status||Published - 2004 Dec 1|
|Event||5th IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS - , Dominican Republic|
Duration: 2004 Nov 3 → 2004 Nov 5
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