Warped-compression: Enabling power efficient GPUs through register compression

Sangpil Lee, Keunsoo Kim, Gunjae Koo, Hyeran Jeon, Won Woo Ro, Murali Annavaram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

64 Citations (Scopus)

Abstract

This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementation-efficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single register, or one of the register banks, as the primary base and then computing delta values of all the other registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing register values, each warp-level register access activates fewer register banks, which leads to reduction in dynamic power. When fewer banks are used to store the register content, leakage power can be reduced by power gating the unused banks. Evaluation results show that register compression saves 25% of the total register file power consumption.

Original languageEnglish
Title of host publicationISCA 2015 - 42nd Annual International Symposium on Computer Architecture, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages502-514
Number of pages13
ISBN (Electronic)9781450334020
DOIs
Publication statusPublished - 2015 Jun 13
Externally publishedYes
Event42nd Annual International Symposium on Computer Architecture, ISCA 2015 - Portland, United States
Duration: 2015 Jun 132015 Jun 17

Publication series

NameProceedings - International Symposium on Computer Architecture
Volume13-17-June-2015
ISSN (Print)1063-6897

Conference

Conference42nd Annual International Symposium on Computer Architecture, ISCA 2015
Country/TerritoryUnited States
CityPortland
Period15/6/1315/6/17

ASJC Scopus subject areas

  • Hardware and Architecture

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