TY - GEN
T1 - Warped-compression
T2 - 42nd Annual International Symposium on Computer Architecture, ISCA 2015
AU - Lee, Sangpil
AU - Kim, Keunsoo
AU - Koo, Gunjae
AU - Jeon, Hyeran
AU - Ro, Won Woo
AU - Annavaram, Murali
N1 - Publisher Copyright:
© 2015 ACM.
PY - 2015/6/13
Y1 - 2015/6/13
N2 - This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementation-efficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single register, or one of the register banks, as the primary base and then computing delta values of all the other registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing register values, each warp-level register access activates fewer register banks, which leads to reduction in dynamic power. When fewer banks are used to store the register content, leakage power can be reduced by power gating the unused banks. Evaluation results show that register compression saves 25% of the total register file power consumption.
AB - This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementation-efficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single register, or one of the register banks, as the primary base and then computing delta values of all the other registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing register values, each warp-level register access activates fewer register banks, which leads to reduction in dynamic power. When fewer banks are used to store the register content, leakage power can be reduced by power gating the unused banks. Evaluation results show that register compression saves 25% of the total register file power consumption.
UR - http://www.scopus.com/inward/record.url?scp=84960096781&partnerID=8YFLogxK
U2 - 10.1145/2749469.2750417
DO - 10.1145/2749469.2750417
M3 - Conference contribution
AN - SCOPUS:84960096781
T3 - Proceedings - International Symposium on Computer Architecture
SP - 502
EP - 514
BT - ISCA 2015 - 42nd Annual International Symposium on Computer Architecture, Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 13 June 2015 through 17 June 2015
ER -