A modified MOS REL structure is proposed, which exhibits the wired-OR property and enhances speed and power characteristics. Proposed MOS REL gates have been fabricated and tested. It is shown that the power x delay product of an MOS REL inverter is enhanced by 26% with a smaller silicon area.
|Number of pages||3|
|Publication status||Published - 1997 Apr 24|
- Logic circuits
- Logic design
ASJC Scopus subject areas
- Electrical and Electronic Engineering